Offset removal circuitry for photoreceiver signals

• US 5,900,625 A
• Filed: 09/05/1997
• Issued: 05/04/1999
• Est. Priority Date: 01/25/1996
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.), Hewlett-Packard Development Company, L.P. (HP Inc.), Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Baumgartner, Richard A.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): PYO, KEVIN K
• Application Number:
  US08/924,161
• Time in Patent Office: 606 Days
• Field of Search: 250/214 C, 250/214 A, 250/214 R, 250/208.1, 327/307, 327/514, 327/515, 327/551, 327/552, 348/241, 348/294, 348/300, 348/308
• US Class Current: 250/214.00C
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 2200/249 A switch coupled in the input circuit of an amplifier being controlled by a circuit, e.g. feedback circuitry being controlling the switch
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/701 Line sensors
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A method for transferring signals from a photoreceiver array to computational circuitry in which parallel transfer amplifiers receive periodic offset correction. In a first embodiment, each transfer amplifier has a differential circuit that can be switched from a reset mode to a readout mode. In the readout mode, the voltage state at the output is responsive to first and second inputs, with the second input being connected to a source of a reference voltage. In the reset mode, the inputs are both connected to the reference voltage and the output is temporarily connected to a source of a fixed reset voltage. An offset adjustment signal is generated in response to detection of a voltage difference between the reset voltage and the actual voltage state at the output after the output has been disconnected from the source of the reset voltage. A single offset circuit is used to periodically and sequentially refresh the various transfer amplifiers.

Claims

1. A method of providing offset correction to a differential circuit that is periodically switched between readout operations and reset operations, said differential circuit having first and second circuit inputs and a circuit output for which an output voltage condition is responsive to voltage states at said circuit inputs, said method being carried out for at least some of said reset operations and said method comprising:

(a) connecting said first circuit input to said second circuit input when said differential circuit is switched from a readout operation to a reset operation;

(b) connecting said circuit output to a source of a fixed voltage state when said differential circuit is switched from said readout operation to said reset operation;

(c) disconnecting said circuit output from said source following a first time segment of said reset operation, thereby initiating a second time segment of said reset operation in which said circuit output is free to float from said fixed voltage state; and

(d) forming an offset correction signal in response to a shift of a voltage condition at said circuit output during said second time segment.

2. The method of claim 1 wherein said steps of disconnecting said circuit output from said source and forming said offset correction signal are carried out for only a portion of said reset operations, said method further comprising storing said offset correction signal for application to said differential circuit during said readout operations.

3. The method of claim 1 wherein said step of connecting said circuit output to a source is a step of connecting said circuit output to a source of a positive voltage.

4. The method of claim 1 wherein said step of forming said offset correction signal includes comparing said fixed voltage state of said source to said voltage condition at said circuit output during said second time segment.

5. The method of claim 1 wherein said step of connecting said first circuit input to said second circuit input is a step of connecting said first and second inputs to a second source of a fixed voltage.

6. The method of claim 1, wherein:

the method additionally comprises;

providing a photoelement array in which photoelements are operationally grouped with respect to transfers of photocurrent signals to computational circuitry, thereby defining a plurality of photoelement groups, one of said photoelement groups being operatively associated with the differential circuit,

connecting the second input of said differential circuit to a source of a reference voltage,

capacitively coupling the first input of said differential circuit to the output of said differential circuit, and

sequentially connecting said photoelements in said one of said photoelement groups to said first input of said differential circuit with which said group is operatively associated, and leaving reset intervals in which none of said photoelements is connected to said inputs; and

said steps (a) through (d) are performed during said reset intervals.

7. The method of claim 6, wherein:

in the step of providing a photoelement array, each photoelement group is a column of photoelements arranged such that said photoelement array has a plurality of columns and rows; and

said differential circuit is operatively associated with the photoelements of a single column.

8. The method of claim 7, further comprising coupling said offset correction signal to said differential circuit during said reset intervals.

9. The method of claim 7, wherein said offset correction signal is formed by subtracting said reset voltage from said output of said differential circuit to provide an error voltage.

10. The method of claim 9, wherein said offset correction signal is additionally formed by holding said error voltage.