Quasi-mesh gate structure for lateral RF MOS devices

• US 5,900,663 A
• Filed: 02/07/1998
• Issued: 05/04/1999
• Est. Priority Date: 02/07/1998
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Xemod, Inc. (Qorvo, Inc.)
• Inventors: Johnson, Joseph Herbert, D'Anna, Pablo Eugenio
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US09/020,256
• Time in Patent Office: 451 Days
• Field of Search: 257/341, 257/343, 257/401, 257/339, 257/162, 257/327, 257/382-384, 257/621, 438/306
• US Class Current: 257/343
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A quasi-mesh gate structure for the RF MOS transistor having a conductive plug source-body-backside connection is disclosed. The RF MOS transistor having the quasi-mesh gate structure utilizes significantly shorter feeding gate paths as compared to the long feeding gate paths used in the prior art RF MOS devices. The RF MOS transistor having the quasi-mesh gate structure can utilize the polysilicon gates or silicided gates. This results in simplification of the fabrication process and/or improved performance at high frequencies.

Claims

1. A lateral RF MOS transistor having a quasi-mesh gate structure comprising:

a semiconductor material of a first conductivity type, said semiconductor material having a first dopant concentration and a top surface;

a conductive gate overlying and insulated from said top surface of said semiconductor material;

a plurality of first regions formed completely within said semiconductor material of said first conductivity type, said first regions being of a second conductivity type and a second dopant concentration to form substantially identical enhanced drain drift regions of said lateral RF MOS transistor, each of said first regions having a first end, wherein said first end of each of said first regions underlies a portion of said conductive gate;

a plurality of second regions formed in said semiconductor material, said second regions being of said second conductivity type and a third dopant concentration greater than said second dopant concentration to form substantially identical drain regions of said lateral RF MOS transistor, wherein each of said second regions contacts a respective one of said first regions, wherein each of said second regions is separated from said conductive gate by a first distance necessary to achieve a first breakdown voltage;

a plurality of third regions formed in said semiconductor material, said third regions being of said first conductivity type and a fourth dopant concentration to form substantially identical body regions of said lateral RF MOS transistor, said fourth dopant concentration being equal or greater than said first dopant concentration, each of said third regions having a first end, wherein said first end of each of said third regions underlies a portion of said conductive gate, any remaining portion of said semiconductor material underlying said gate being of said first conductivity type;

a plurality of fourth regions formed in said semiconductor material, each of said fourth regions being of said second conductivity type and a fifth dopant concentration to form substantially identical source regions of said lateral RF MOS transistor, each of said fourth regions located within a respective one of said third regions, and wherein each of said fourth regions underlies a portion of said gate;

a plurality of fifth regions formed in said semiconductor material, each of said fifth regions being of said first conductivity type and a sixth dopant concentration to form substantially identical body contact enhancement regions of said lateral RF MOS transistor, said sixth dopant concentration being greater than said fourth dopant concentration, each of said fifth regions being located within a respective one of said third regions;

a plurality of conductive plug regions, each said conductive plug region being formed in a respective one of said source regions and said body regions, each said conductive plug region being used to connect one said source region and one said body region of said semiconductor material to a backside of said lateral RF MOS transistor;

a layer of an insulator covering said top surface of said semiconductor material, said insulator layer including a first plurality of openings and a second plurality of openings;

said first plurality of openings used to expose said gate;

said second plurality of openings used to expose each said drain region;

a first plurality of metal fingers used to connect each said exposed drain region to a first side of said RF MOS transistor; and

a second plurality of metal fingers used to connect said exposed gate region to a second side of said RF MOS transistor;

wherein the usage of said plurality of conductive plug regions allows to make a low resistance connection between said plurality of source areas and said backside of a substrate of said lateral RF MOS transistor.

2. The lateral RF MOS transistor of claim 1, wherein said first conductivity type is a P type.

3. The lateral RF MOS transistor of claim 1, wherein at least one said conductive plug region comprises a metal plug region.

4. The lateral RF MOS transistor of claim 1, wherein at least one said conductive plug region comprises a silicided plug region.

5. The lateral RF MOS transistor of claim 4, wherein said at least one silicided plug region comprises a tungsten silicided plug region.

6. The lateral RF MOS transistor of claim 4, wherein said at least one silicided plug region comprises a titanium silicided plug region.

7. The lateral RF MOS transistor of claim 4, wherein said at least one silicided plug region comprises a cobalt silicided plug region.

8. The lateral RF MOS transistor of claim 4, wherein said at least one silicided plug region comprises a platinum silicided plug region.

9. A lateral RF MOS transistor having a top quasi-mesh gate structure comprising:

a conductive gate having a plurality of substantially identical gate sites in said top quasi-mesh gate structure;

a plurality of substantially identical drain regions, each of said drain regions having a substantially identical drain site in said top quasi-mesh gate structure;

a plurality of substantially identical source regions;

a plurality of substantially identical body regions;

wherein each of said drain regions is separated from said conductive gate by a first distance necessary to achieve a first breakdown voltage; and

wherein each of said body regions underlies a portion of said conductive gate; and

wherein each of said source regions is located within a respective one of said body regions, and wherein each of said source regions underlies a portion of said gate;

a plurality of substantially identical conductive plug regions, each of said conductive plug regions being formed in a respective one of said source regions and in one of said body regions, each of said conductive plug regions being used to connect one said source region and one said body region to a backside of said lateral RF MOS transistor;

a first plurality of metal fingers used to connect each said drain site to a first side of said RF MOS transistor; and

a second plurality of metal fingers used to connect each said gate site to a second side of said RF MOS transistor.

10. The lateral RF MOS transistor of claim 9, wherein at least one said substantially identical gate site approximates a diamond shape.

11. The lateral RF MOS transistor of claim 9, wherein at least one said substantially identical gate site approximates a circular shape.

12. The lateral RF MOS transistor of claim 9, wherein at least one said substantially identical drain site approximates a square shape.

13. The lateral RF MOS transistor of claim 9, wherein at least one said substantially identical drain site approximates a diamond shape.

14. The lateral RF MOS transistor of claim 9, wherein at least one said substantially identical drain site approximates a circular shape.