Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs

• US 5,900,746 A
• Filed: 06/13/1996
• Issued: 05/04/1999
• Est. Priority Date: 06/13/1996
• Status: Expired due to Term

• Current Assignee: Swayze W. Daniel Jr
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sheahan, Benjamin Joseph
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/664,095
• Time in Patent Office: 1,055 Days
• Field of Search: 326/64, 326/66, 326/73, 326/77
• US Class Current: 326/73
• CPC Class Codes: H03K 19/017527 with at least one differential stage

Abstract

A pair of complementary signals are switched between a high state and a low state such that the complementary signals are switched within a time period less than two gate delays. An inverter biases other inverters so that these two inverters are maintained at their threshold levels. The maintenance at the threshold values enable these two inverters to be switched quickly.

Claims

1. A level shifting circuit for switching a first complementary signal and a second complementary signal, comprising:

an input circuit including a first transistor to receive said first complementary signal and said second complementary signal; and

a switching circuit coupled to said input circuit to switch said first complementary signal and said second complementary signal between a high state and a low state, said level shifting circuit including a second transistor coupled to said input circuit, wherein said switching circuit switches said first complementary signal and said second complementary signal within a time period of two gate delays based on said first and second transistors.

2. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 1, wherein said first complementary signal and said second complementary signal alternate between a first level when received by said input circuit and a second level.

3. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 1, wherein said first complementary signal and said second complementary signal are switched between said high state and a low state within 1.4 nano seconds.

4. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 1, wherein said transistors are coupled to a common node voltage.

5. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 4, wherein said transistors are coupled to a common node voltage of substantially 1 volt.

6. A level shifting circuit for switching between a first complementary signal and a second complementary signal, comprising:

an input circuit to receive said first complementary signal with respect to a first level and said second complementary signal with respect to said first level;

a switch coupled to said input circuit to switch said first complementary signal and said second complementary signal between a high state and a low state;

an inverting circuit coupled to said switch to maintain an output of said inverting circuit at a threshold voltage of said switch;

a pair of voltage limiting devices coupled to said output of said inverting circuit and coupled to said switch to output said first and second complementary signals at a second level.

7. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 6, wherein said first level is lower than said second level.

8. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 6, wherein said first level is substantially 1 volt.

9. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 6, wherein said second level is substantially 5 volts.

10. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 6, wherein said output of said inverting circuit is directly coupled to an input of said inverting circuit.

11. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 6, wherein said pair of voltage limiting devices are resistors.

12. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 11, wherein said resistors have substantially the same resistance.

13. A level shifting circuit for switching between a first complementary signal and a second complementary signal as in claim 6, wherein each of said voltage limiting devices are coupled to a transistor.