Method of driving a liquid crystal display device and a driving circuit for the liquid crystal display device

• US 5,900,857 A
• Filed: 05/17/1996
• Issued: 05/04/1999
• Est. Priority Date: 05/17/1995
• Status: Expired due to Term

• Current Assignee: Optrex Corporation (Kyocera Corporation)
• Original Assignee: Asahi Glass Company, Limited (AGC, Inc.)
• Inventors: Hirai, Yoshinori, Kawaguchi, Kazuyoshi, Kuwata, Takeshi
• Primary Examiner(s): Mengistu, Amare
• Application Number:
  US08/648,960
• Time in Patent Office: 1,082 Days
• Field of Search: 345/100, 345/103, 345/200, 345/203, 345/98, 345/508, 345/516, 345/517
• US Class Current: 345/100
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3625 using active addressing
• CPC Class Codes: G09G 3/3644 with the matrix divided into sections

Abstract

A method of driving a liquid crystal display device by selecting simultaneously a plurality of lines in a liquid crystal display element characterized in that display data are temporality stored in memories; the data are read out plural times from the memories, and arithmetic operation are performed to the read-out data to produce signals to be applied to data electrodes, wherein the picture area is divided into a plurality of picture area blocks each including scanning lines the number of which are a multiple of a natural number of simultaneously selected scanning lines; the memories are divided into a plurality of memory blocks each having capacity capable of reading and writing data displayed on the picture area blocks; fames for writing are made in synchronism with frames for reading the data, and a memory block undergoes a predetermined number of times of reading, and then new display data are written into said memory block.

Claims

1. A method of driving a display device having a plurality of scanning lines and a plurality of data lines comprising the steps of:

selecting simultaneously a first group of said plurality of scanning lines in said device;

dividing a single matrix picture area into a plurality of picture area blocks, each one of said plurality of picture area blocks including a second group of said plurality of scanning lines, wherein a number of said second group of said plurality of scanning lines is an integral multiple of a number of said first group of said plurality of scanning lines, wherein said single matrix picture area includes said plurality of scanning lines and said plurality of data lines;

dividing each one of at least one memory into a plurality of memory blocks, wherein each one of said plurality of memory blocks has sufficient capacity to store all reading and writing data displayed on each one of said plurality of picture area blocks, and said each one of said plurality of memory blocks is accessible in parallel;

writing display data in said each one of said at least one memory;

reading out said display data from said each one of said at least one memory; and

performing at least one arithmetic operation on display data which has been read out by said step of reading out to produce a plurality of signals to be applied to said plurality of data lines, wherein

a first plurality of frames for writing said display data are synchronized with a second plurality of frames for reading said display data, and

each one of said plurality of memory blocks undergoes reading a predetermined number of times before new display data are written into said each one of said plurality of memory blocks.

2. The method according to claim 1, wherein

said single matrix picture area is scanned by one continuous scanning operation;

a length of each one of said first plurality of frames is an integral multiple of a length of each one of said second plurality of frames; and

a number of said plurality of memory blocks is at least one greater than a number which is a sufficient memory capacity for receiving data to be written in a memory within one of said second plurality of frames from said at least one memory.

3. The method according to claim 1, wherein

an upper portion and a lower portion of said single matrix picture area are driven respectively by independent scanning;

a length of each one of said first plurality of frames is an integral multiple of a length of each one of said second plurality of frames; and

a number of said plurality of memory blocks is at least two greater than a number which is a sufficient memory capacity for receiving data written in a memory within one of said second plurality of frames from said at least one memory.

4. The method according to claim 3, wherein

said length of each one of said first plurality of frames is twice said length of each one of said second plurality of frames, and

each one of said at least one memory includes three regions, and each one of said three regions includes a group of said plurality of memory blocks wherein a number of said group of said plurality of memory blocks is larger than a number of a group of said plurality of picture area blocks at a side of said device.

5. The method according to claim 4, wherein

picture image data displayed in an upper portion and a lower portion of said device are stored in a first one of said three regions of one of said plurality of memories;

picture image data displayed in said upper portion of said device are stored in a second one of said three regions, wherein said first one of said three regions is different from said second one of said three regions, and

picture image data displayed in said lower portion of said device are stored in a third one of said three regions, wherein said third one of said three regions is different from said second one of said three regions and from said first one of said three regions.

6. The method according to claim 3, wherein

said length of each one of said first plurality of frames is twice said length of each one of said second plurality of frames;

each one of said plurality of memories has, a first region including a first group of said plurality of memory blocks, said first group of said plurality of memory blocks having a number of said plurality of memory blocks which is one greater than a number of said plurality of picture area blocks, and a second region including a second group of said plurality of memory blocks wherein a number of said second group of said plurality of memory blocks is one greater than twice a number of said plurality of picture area blocks of said device.

7. The method according to claim 6, wherein picture image data of an odd number of said first plurality of frames and said second plurality of frames are stored in a first plurality of display frames, in one of said first region and said second region, and picture image data of an even number of said first plurality of frames and said second plurality of frames are stored in a second plurality of display frames, in a different one of said first region and said second region.

8. The method according to claim 1, wherein a plurality of clock signals which are in synchronism with input picture image data inputted to said at least one memory are used for synchronizing the writing of data into said at least one memory with the reading of the data from said at least one memory and with a timing to an electrode driving means.

9. The method according to claim 8, wherein said plurality of clock signals in synchronism with the input picture image data are counted, and when a counted value for a row electrode driving time reaches a predetermined value, a judgment of row electrode driving time is provided.

10. The method according to claim 8, wherein a reference time point for a timing operation is determined when a predetermined time has passed after a vertical synchronizing signal has been inputted.

11. The method according to claim 10, wherein said reference time point is determined at an input time point of a horizontal synchronizing signal which is intermediate in all horizontal synchronizing signals in one frame of said first plurality of frames and said second plurality of frames, after the vertical synchronizing signal has been inputted.

12. A driving circuit for a display device, aid display device having a plurality of scanning lines and a plurality of data lines comprising:

at least one memory for temporarily storing input picture image data, each one of said at least one memory including a plurality of memory blocks, each one of said plurality of memory blocks having sufficient capacity to store all reading and writing data to be displayed on each one of a plurality of picture area blocks, said plurality of picture area blocks formed by dividing a single matrix picture area, each one of said plurality of picture area blocks including a group of said plurality of scanning lines wherein a number of said group of said plurality of scanning lines is an integral multiple of a number of simultaneously selected ones of said plurality of scanning lines, wherein said single matrix picture area includes said plurality of scanning lines and said plurality of data lines,

a timing control means for synchronizing a first plurality of frames for writing data in said at least one memory with a second plurality of frames for reading the data from said at least one memory, and

a memory control means for controlling writing new display data in each one of said plurality of memory blocks in parallel after each one of said plurality of memory blocks undergoes reading a predetermined number of times necessary for arithmetic operation for producing a plurality of data signals.

13. The driving circuit according to claim 12, wherein aid driving circuit is adapted to scan said single matrix picture area by one continuous scanning operation;

said timing control means controls so that a length of each one of said first plurality of frames is an integral multiple of each one of said second plurality of frames; and

a number of said plurality of memory blocks is at least one greater than a number which is a sufficient memory capacity for receiving data to be written in a memory within one of said second plurality of frames from said at least one memory.

14. The driving circuit according to claim 12, wherein

said driving circuit is so adapted that an upper portion and a lower portion of said single matrix picture area are scanned respectively by independent scanning operations;

said timing control means controls so that a length of each one of said first plurality of frames is an integral multiple of a length of each one of said second plurality of frames; and

a number of said plurality of memory blocks is at least two greater than a number which is a sufficient memory capacity for receiving data to be written in a memory within one of said second plurality of frames from said at least one memory.

15. The driving circuit according to claim 14, wherein

said timing control means is so adapted that said length of each one of said first plurality of frames is twice said length of each one of said second plurality of frames;

each one of said at least one memory includes three regions, and each one of said three regions includes a group of said plurality of memory blocks wherein a number of said group of said plurality of memory blocks is larger than a number of said plurality picture area blocks of said device, and

a memory control means controls so that picture image data displayed in an upper portion and a lower portion of said device are stored in a first one of said three regions of one of said plurality of memories;

picture image data displayed in said upper portion of said device are stored in a second one of said three regions, wherein said first one of said three regions is different from said second one of said three regions, and

picture image data displayed in said lower portion of said device are stored in a third one of said three regions wherein said third one of said three regions is different from said second one of said three regions and from said first one of said three regions.

16. The driving circuit according to claim 14, wherein said timing control means is so adapted that said length of each one of said first plurality of frames is twice said length of each one of said second plurality of frames;

each one of said plurality of memories has, a first region including a first group of said plurality of memory blocks, said first group of said plurality of memory blocks having a number of said plurality of memory blocks which is one greater than a number of said plurality of picture area blocks, and a second region including a second group of said plurality of memory blocks wherein a number of said second group of said plurality of memory blocks is one greater than twice a number of said plurality of picture area blocks of said device; and

a memory control means stores picture image data of an odd number of said first plurality of frames and said second plurality of frames in a first plurality of display frames, in one of said first region and said second region, and said memory control means stores picture image data of an even number of frames in a second plurality of display frames, in a different one of said first region and said second region.

17. The driving circuit according to claim 12, wherein said timing control means is so adapted that a plurality of clock signals which are in synchronism with input picture image data inputted to said at least one memory are used for synchronizing the writing of data into said at least one memory with the reading of the data from said at least one memory and with a timing to an electrode driving means.

18. The driving circuit according to claim 17, wherein the timing control means includes an arithmetic circuit for providing a value for determining a row electrode driving time, and is so adapted that said plurality of clock signals in synchronism with the input picture image data are counted, and when a counted value reaches a predetermined value for a row electrode driving time, a judgment of row electrode driving time is provided.

19. The driving circuit according to claim 17, wherein a reference time point for a timing operation is determined when a predetermined time has passed after a vertical synchronizing signal has been inputted.

20. The driving circuit according to claim 19, wherein the timing control means is so adapted that said reference time point is determined at an input time point of a horizontal synchronizing signal which is intermediate in all horizontal synchronizing signals in one frame of said first plurality of frames and said second plurality of frames, after the vertical synchronizing signal has been inputted.