Display controller capable of accessing an external memory for gray scale modulation data

• US 5,900,886 A
• Filed: 05/26/1995
• Issued: 05/04/1999
• Est. Priority Date: 05/26/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Shay, Michael John
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): CHANG, KENT WU
• Application Number:
  US08/451,319
• Time in Patent Office: 1,439 Days
• Field of Search: 345/147, 345/148, 345/89, 345/98, 345/99, 345/185, 345/189, 345/190, 345/200, 345/203, 345/511, 345/508, 345/509, 345/513, 345/516, 395/164, 395/166, 84/627
• US Class Current: 345/691
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A display controller includes a data bus interface which transfers data to the display controller from external sources. A modulation data register coupled to the data bus interface receives a first quantity of modulation data through the data bus interface. A decoder coupled to the modulation data register receives the first quantity of modulation data and decodes graphics data according to the first quantity of modulation data in order to generate display data. A modulation data address counter counts quantities of modulation data that are transferred through the data bus interface and generates a load modulation data signal when a preprogrammed total quantity of modulation data has been transferred through the data bus interface. A method used by a display controller of accessing modulation data from an external memory is also disclosed.

Claims

1. A display controller, comprising:

a data bus interface configured to receive modulation data from a designated space in an external memory which is allocated to store modulation data;

a modulation data register coupled to the data bus interface and configured to receive a first quantity of modulation data through the data bus interface from the designated space in the external memory;

a decoder coupled to the modulation data register and configured to receive the first quantity of modulation data and to decode graphics data according to the first quantity of modulation data in order to generate display data; and

a modulation data address counter coupled to the data bus interface and having an input configured to set a preprogrammed total quantity of modulation data which corresponds to a size of the designated space in the external memory which is allocated to store modulation data, the modulation data address counter configured to count quantities of modulation data that are transferred through the data bus interface and to generate a load modulation data signal when the preprogrammed total quantity of modulation data has been transferred through the data bus interface to indicate that the designated space in the external memory needs to be updated.

2. A display controller in accordance with claim 1, further comprising:

a configuration register, coupled to the input of the modulation data address counter, which is used to set the preprogrammed total quantity of modulation data.

3. A display controller in accordance with claim 1, further comprising:

a direct memory access (DMA) interface control block which generates a data request signal which is used to initiate transfer of the first quantity of modulation data through the data bus interface.

4. A display controller, comprising:

a data bus interface for transferring data to the display controller from external sources;

a modulation data register coupled to the data bus interface which receives a first quantity of modulation data through the data bus interface;

a decoder coupled to the modulation data register which receives the first quantity of modulation data and decodes graphics data according to the first quantity of modulation data in order to generate display data;

a modulation data address counter which counts quantities of modulation data that are transferred through the data bus interface and which generates a load modulation data signal when a preprogrammed total quantity of modulation data has been transferred through the data bus interface; and

an interrupt generation circuit coupled to the modulation data address counter which generates a CPU interrupt in response to the load modulation data signal.

5. A display controller, comprising:

a data bus interface for transferring data to the display controller from external sources;

a direct memory access (DMA) interface control block which generates a data request signal which is used to initiate transfer of a first quantity of modulation data through the data bus interface;

a modulation data register coupled to the data bus interface which receives the first quantity of modulation data;

a decoder coupled to the modulation data register which receives the first quantity of modulation data and decodes graphics data according to the first quantity of modulation data in order to generate display data;

a modulation data address counter which counts quantities of modulation data that are transferred through the data bus interface and which generates a load modulation data signal when a preprogrammed total quantity of modulation data has been transferred through the data bus interface; and

an interrupt generation circuit coupled to the modulation data address counter which generates a CPU interrupt in response to the load modulation data signal.

6. A display controller in accordance with claim 5, wherein the modulation data address counter further comprises:

an input which is used for setting the preprogrammed total quantity of modulation data, the preprogrammed total quantity of modulation data indicating an amount of space in an external memory which is allocated to store modulation data.

7. A display controller in accordance with claim 6, further comprising:

a configuration register, coupled to the input of the modulation data address counter, which is used to set the preprogrammed total quantity of modulation data.

8. A method used by a display controller of accessing modulation data from an external memory, comprising the steps of:

generating a data request signal which initiates transfer of a first quantity of modulation data to the display controller from an external memory;

receiving the first quantity of modulation data in a modulation data register;

transferring the first quantity of modulation data to a decoder;

decoding graphics data according to the first quantity of modulation data in order to generate display data;

counting quantities of modulation data that are transferred to the display controller;

generating a load modulation data signal in response to a preprogrammed total quantity of modulation data being transferred to the display controller; and

generating a CPU interrupt in response to the load modulation data signal.

9. A method in accordance with claim 8, further comprising the step of:

setting the preprogrammed total quantity of modulation data.