Pulse-width-modulation control circuit

• US 5,901,054 A
• Filed: 12/18/1997
• Issued: 05/04/1999
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: National Chung-Shan Institute of Science and Technology
• Original Assignee: Chung-Shan Institute of Science and Technology Armaments Bureau Ministry of National Defense
• Inventors: Leu, Ching-Shan, Liu, Wueichan, Hwang, Jeang
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Patel, Rajnikant B.
• Application Number:
  US08/993,297
• Time in Patent Office: 502 Days
• Field of Search: 363/41, 363/95, 363/26, 363/131, 363/97, 363/132, 327/254
• US Class Current: 363/41
• CPC Class Codes: H02M 3/285 Single converters with a plurality of output stages connected in parallel parallel operation of a plurality of converters in dc distribution networks H02J1/10

Abstract

A PWM controlling circuit includes a signal generator and two PWM controllers. The signal generator comprises an oscillator, a plurality of inverters, and two RC delay networks. The oscillator and the inverters are composed of elementary elements, respectively, such as diodes, resistors, inverters and capacitors. The PWM controlling circuit in accordance with the present invention can be implemented with low cost, and the duty cycles thereof are not limited to 50%.

Claims

1. A pulse width modulation (PWM) controlling circuit comprising:

an oscillator having a first output and a second output for outputting two synchronous signals with a predetermined phase shift therebetween;

a first RC delay network and a second RC delay network respectively connected to said first and second outputs of said oscillator, said first and second RC delay networks generating two narrow pulses with said predetermined phase shift therebetween;

a first PWM controller connected with said first RC delay network to receive one of said two narrow pulses to be triggered thereby; and

a second PWM controller connected with said second RC delay network to receive the other of said two narrow pulses to be triggered thereby.

2. The PWM controlling circuit as claimed in claim 1, further comprising two inverters, one of which is connected between said first output of the oscillator and said first RC delay network, the other one is connected between said second output of the oscillator and said second RC delay network.

3. The PWM controlling circuit as claimed in claim 2, further comprising another two inverters, one of which is connected between said first RC delay network and said first PWM controller, and the other one is connected between said second RC delay network and said second PWM controller.

4. The PWM controlling circuit as claimed in claim 1, further comprising two inverters, one of which is connected between said first RC delay network and said first PWM controller, and the other one is connected between said second RC delay network and said second PWM controller.

5. The PWM controlling circuit as claimed in claim 1, wherein said oscillator comprises two diodes, two inverters, two resistors and a capacitor.

6. The PWM controlling circuit as claimed in claim 1, wherein each of said first and second RC delay networks comprises a diode, a capacitor and a resistor.