Semiconductor structure design and process visualization through the use of simple process models and intuitive interfaces
First Claim
1. A method for visualizing a semiconductor design and process, comprising the steps of:
- providing a plurality of abstract process models having only a plurality of physical parameter inputs;
providing a menu for adding, deleting, and editing a plurality of process steps using said plurality of abstract process models;
displaying said plurality of process steps in a process flow window and allowing for the selection of one of said process steps; and
displaying a cross-section of a wafer at said selected process step in a cross-section window.
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Accused Products
Abstract
A semiconductor structure design and process visualization tool (10). A main menu (30) allows a user to add, edit or delete process steps (16a-f) to create a process flow in process flow window (12). Main menu (30) provides a set of process models to be selected from. The set of process models are simple first-order geometric models that require only physical parameters of a resulting device layer. Specific process conditions are not required. Semiconductor process and wafer representation tool applies the physical parameters to the corresponding process model to quickly create a cross-section (20) in cross-section window (22) corresponding to a selected process step (16d) in process flow window (12).
70 Citations
15 Claims
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1. A method for visualizing a semiconductor design and process, comprising the steps of:
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providing a plurality of abstract process models having only a plurality of physical parameter inputs; providing a menu for adding, deleting, and editing a plurality of process steps using said plurality of abstract process models; displaying said plurality of process steps in a process flow window and allowing for the selection of one of said process steps; and displaying a cross-section of a wafer at said selected process step in a cross-section window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for visualizing a semiconductor device structure and process, comprising the steps of:
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receiving a first process step input including only a first plurality of physical characteristics of a first device layer; creating a first semiconductor process and wafer representation (SPWR) for said first process step using said first plurality of physical characteristics; displaying said first semiconductor process and wafer representation; receiving a second process step input including only a second plurality of physical characteristics for a second device layer; creating a second SPWR for said first and second process steps; displaying said second SPWR; receiving instructions to alter said first device layer; automatically altering both said first and second SPWRs in response to said instructions; and redisplaying said first SPWR. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification