Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources

• US 5,901,307 A
• Filed: 07/22/1996
• Issued: 05/04/1999
• Est. Priority Date: 07/22/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: International Business Machines Corporation, Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rossbach, Paul Charles, Thomas, Thomas Luther Jr., Potter, Terence Matthew
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PATEL, GAUTAM
• Application Number:
  US08/684,720
• Time in Patent Office: 1,016 Days
• Field of Search: 395/383, 395/376, 395/800.23, 395/586, 395/587, 395/585
• US Class Current: 712/240
• CPC Class Codes: G06F 9/3848 using hybrid branch prediction, e.g. selection between prediction techniques

Abstract

A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

Claims

1. A method within a processor of speculatively executing a branch instruction, said processor including a branch prediction unit, said method comprising:

storing a plurality of branch predictions, wherein each of said plurality of branch predictions has an associated bit pattern;

detecting a speculative branch instruction;

in response to a detection of a speculative branch instruction, deriving each bit within an access bit pattern from a source among a plurality of sources, wherein bits within said access bit pattern are derived from two or more sources among said plurality of sources;

accessing one of said plurality of branch predictions utilizing said access bit pattern; and

in response to said accessed branch prediction, calculating a target address.

2. The method of claim 1, and further comprising the step of storing branch history of at least one previously executed branch instruction.

3. The method of claim 2, wherein said plurality of sources include an address of said speculative branch instruction and said branch history of at least one previously executed branch instruction.

4. The method of claim 1, and further comprising the step of automatically determining a source among said plurality of sources for each bit within said access bit pattern.

5. The method of claim 4, wherein said step of automatically determining a source among said plurality of sources for each bit within said access bit pattern is performed dynamically during execution of instructions.

6. The method of claim 4, wherein said step of automatically determining a source among said plurality of sources for each bit within said access bit pattern is performed in response to an indication of branch prediction accuracy.

21. The method of claim 2, wherein storing branch history of at least one previously executed branch instruction comprises:

storing branch history of K most recently executed branch instructions in a global branch history register.

7. A processor, comprising;

means for storing a plurality of branch predictions, wherein each of said plurality of branch predictions has an associated bit pattern;

means for detecting a speculative branch instruction;

means for deriving each bit within an access bit pattern from a source among a plurality of sources in response to a detection of a speculative branch instruction, wherein bits within said access bit pattern are derived from two or more sources among said plurality of sources;

means for accessing one of said plurality of branch predictions utilizing said access bit pattern; and

means for calculating a target address in response to said accessed branch prediction.

8. The processor of claim 7, and further comprising means for storing branch history of at least one previously executed branch instruction.

9. The processor of claim 8, wherein said plurality of sources include an address of said speculative branch instruction and said branch history of at least one previously executed branch instruction.

10. The processor of claim 7, and further comprising means for automatically determining a source among said plurality of sources for each bit within said access bit pattern.

11. The processor of claim 10, wherein said means for automatically determining a source among said plurality of sources for each bit within said access bit pattern comprises means for dynamically determining a source among said plurality of sources for each bit within said access bit pattern during execution of instructions.

12. The processor of claim 10, wherein said means for automatically determining a source among said plurality of sources for each bit within said access bit pattern determines a source among said plurality of sources for each bit within said access bit pattern in response to an indication of branch prediction accuracy.

22. The processor of claim 8, and wherein said means for storing branch history of at least one previously executed branch instruction comprises:

a global branch history register that stores branch history of K most recently executed branch instructions.

13. A processor, comprising:

branch history storage for storing branch history of at least one previously executed branch instruction;

a branch prediction unit for predicting a resolution of a speculative branch instruction, wherein said branch prediction unit is selectively configurable such that resolution of said speculative branch instruction is predicted in response to an address of said speculative branch instruction and in response to said branch history of at least one previously executed branch instruction; and

an address calculation unit for determining a target address in response to said predicted resolution of said speculative branch instruction.

14. The processor of claim 13, wherein said branch prediction unit is further selectively configurable such that resolution of said speculative branch instruction is predicted in response to said address of said speculative branch instruction and said branch history of at least one previously executed branch instruction.

15. The processor of claim 14, and further comprising branch prediction storage for storing a plurality of predicted resolutions of branch instructions, wherein each of said plurality of predicted resolutions has an associated bit pattern.

16. The processor of claim 15, wherein said branch prediction unit determines a predicted resolution of said speculative branch instruction by selecting a particular bit pattern among said plurality of bit patterns in accordance with a selected configuration of said branch prediction unit.

17. The processor of claim 16, wherein a first number of bits within said particular bit pattern are selected bits within said address of said speculative branch instruction and a second number of bits within said particular bit pattern are indicative of said branch history of at least one previously executed branch instructions.

18. The processor of claim 13, and further comprising means for automatically configuring said branch prediction unit.

19. The processor of claim 18, wherein said means for automatically configuring said branch prediction unit comprises configuration logic for dynamically configuring said branch prediction logic.

20. The processor of claim 19, said configuration logic including an indication of branch prediction accuracy, wherein said configuration logic automatically configures said branch prediction unit in response to said indication of branch prediction accuracy.

23. The processor of claim 13, wherein said branch history storage for storing branch history of at least one previously executed branch instruction comprises a global branch history register that stores branch history of K most recently executed branch instructions.