Float register spill cache method, system, and computer program product

• US 5,901,316 A
• Filed: 07/01/1996
• Issued: 05/04/1999
• Est. Priority Date: 07/01/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Goebel, Kurt J.
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): Nguyen, Cuong H.
• Application Number:
  US08/673,521
• Time in Patent Office: 1,037 Days
• Field of Search: 395/800.23, 395/569, 395/563, 395/393, 395/800.41, 395/394, 395/566, 395/588, 395/674, 395/678, 395/705, 395/562, 395/800.32, 395/580, 395/672, 395/677, 711/202, 711/117, 711/118, 364/715.03, 364/748.16, 364/748.19, 364/748.13, 364/749
• US Class Current: 717/158
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache

Abstract

A float register spill cache method for improving the efficiency of usage of floating point single precision registers computer using a microprocessor conforming to the SPARC-V9 architecture specification. Values are temporarily stored in a plurality of double precision registers which are utilized as a float spill cache having a plurality of float spill slots. Values are generally shifted from one of the single precision registers to a second single precision register which is used as a spill pad, and then from the spill pad to a selected one of the float spill slots.

Claims

1. A computer system having a central processing unit (CPU) and a random access memory coupled to the CPU, for use in compiling a target program to run on a target computer architecture having a fixed number of low precision registers and a fixed number of high precision registers, a selected number of the fixed number of low precision registers forming a spill pad, a selected number of the fixed number of high precision registers forming a spill slot, the computer system comprising:

a compiler system resident in said computer system having a front end compiler, a code optimizer and a back end code generator, wherein

said code optimizer is configured to insert instructions in the target program to spill the low precision registers to the high precision registers through the spill pad and the spill slot.

2. The computer system of claim 1, wherein:

the instructions to spill the low precision register to the high precision registers include an instruction to move data from the low precision register to the spill pad and an instruction to move data from the spill pad to the spill slot.

3. The computer system of claim 2, wherein:

the spill pad is designated one of the low precision registers and associated with a corresponding one of the high precision registers in the spill slot.

4. The computer system of claim 1, wherein:

the low precision registers of the spill pad each coincide with half of a high precision register in the spill slot.

5. The computer system of claim 1, wherein:

said instructions to spill the low precision registers to the high precision registers include a first instruction to move data from a first low precision register to a selected plurality of the low precision registers in the spill pad and a second instruction to move data from the selected plurality of low precision registers to one of the high precision registers.

6. A computer system having a central processing unit (CPU) and a random access memory coupled to the CPU, for use in compiling a target program to run on a target computer architecture having a fixed number of low precision registers and a fixed number of high precision registers, a portion of the low precision registers forming a spill pad, a portion of the high precision forming a spill slot, the computer system comprising:

a compiler system resident in said computer system having a front end compiler, a code optimizer and a back end code generator; and

wherein said code optimizer is configured to insert instructions in the target program to spill the low precision registers to the high precision registers,

wherein said instructions to spill the low precision registers to the high precision registers include a first instruction to move data from a first low precision register to a selected plurality of the low precision registers in the spill pad and a second instruction to move data from the selected plurality of low precision registers to one of the high precision registers, and

the compiler system further inserts an instruction between the first instruction and the second instruction to move data from the one high precision register to the selected plurality of low precision registers and then to a second single precision register.

7. A computer system, having a central processing unit (CPU) and a random access memory coupled to the CPU, for use in compiling a target program to run on a target computer architecture having a fixed number of low precision registers and a fixed number of high precision registers, a selected number of the fixed number of low precision registers forming a spill pad, a selected number of the fixed number of high precision registers forming a spill slot, the computer system comprising:

a compiler system resident in said computer system having a front end compiler, a code optimizer and a back end code generator,

wherein said code optimizer is configured to insert instructions in the target program to spill the low precision registers to the high precision registers

wherein said code optimizer is further configured to insert instructions in the target program to retrieve data from the high precision registers to the low precision registers.

8. An allocated computer register set enabled by computer program code, comprising:

a plurality of single precision registers;

a plurality of double precision registers configured to act as temporary data locations for said single precision registers; and

at least one spill pad having a pair of single precision registers capable of acting together as a double precision register, said spill pad being an adjacent pair of said single precision registers,

wherein data is moved from one of said plurality of single precision registers to said spill pad, and then from said spill pad to one of said double precision registers.

9. The allocated computer register set of claim 8, wherein:

said spill pad is an adjacent pair of said single precision registers.

10. A method for moving data in a computer having a fixed number of low precision registers and a fixed number of high precision registers, a selected number of the fixed number of low precision registers forming a spill pad, a selected number of the fixed number of high precision registers forming a spill slot, comprising:

a) spilling data from the low precision register to the high precision register; and

b) retrieving data from said high precision register to said low precision register

wherein step a includes;

a move value to spill pad operation wherein data is moved from one of the low precision registers to the spill pad; and

a spill to spill slot operation wherein data is moved from the spill pad to the spill slot.

11. The method of claim 10, wherein:

the spill pad is a selected pair of the low precision registers; and

the spill slot is a selected high precision register associated with the selected pair of the low precision registers.

12. The method of claim 10, wherein:

prior to step a), data is moved from the spill slot to the spill pad.

13. The method of claim 10, wherein:

said low precision register is a single precision floating point register; and

said high precision register is a double precision floating point register.

14. A method for moving data in a computer having a low precision register and a high precision register comprising:

a) spilling data from the low precision register to the high precision register; and

b) retrieving data from said high precision register to said low precision register

wherein step b includes;

a retrieve from spill slot operation wherein data is moved from a spill slot to a spill pad; and

a retrieve from spill pad operation wherein data is moved from a spill pad to a low precision register.

15. The method of claim 14, wherein:

the spill pad is a selected pair of low precision registers; and

the spill slot is a selected high precision register.

16. A method for moving data in a computer having a low precision register and a high precision register comprising:

a) spilling data from the low precision register to the high precision register; and

b) retrieving data from said high precision register to said low precision register

wherein step b includes;

a move from spill slot to register operation wherein data is moved directly from the spill slot to a low point register, the spill slot being a high precision register.

17. A method for moving data in a computer having a fixed number of low precision registers and a fixed number of high precision registers, a selected number of the fixed number of low precision registers forming a spill pad, a selected number of the fixed number of high precision registers forming a spill slot, the method comprising:

a) spilling data from the low precision register to the high precision register; and

b) retrieving data from said high precision register to said low precision register

wherein step a includes;

a move value to spill slot operation wherein data is moved directly from a low precision register to a high precision register.

18. An allocated computer register set enabled by computer program code, comprising:

a plurality of single precision registers;

a plurality of double precision registers configured to act as temporary data locations for said single precision registers; and

at least one spill pad having a pair of single precision registers capable of acting together as a double precision register, said spill pad being an adjacent pair of said single precision registers, wherein said spill pad is an adjacent pair of said single precision registers.

19. A computer program product, comprising:

a computer storage medium and a computer program code mechanism embedded in the computer storage medium for causing a computer increase the execution speed of a target computer program, the computer program code mechanism comprising;

a first computer code device configured to determine when virtual registers need to be spilled, said virtual registers comprising said at least one of said low precision registers; and

a second computer code device configured to spill virtual registers to the high precision register through the spill pad and the spill slot.