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Float register spill cache method, system, and computer program product

  • US 5,901,316 A
  • Filed: 07/01/1996
  • Issued: 05/04/1999
  • Est. Priority Date: 07/01/1996
  • Status: Expired due to Term
First Claim
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1. A computer system having a central processing unit (CPU) and a random access memory coupled to the CPU, for use in compiling a target program to run on a target computer architecture having a fixed number of low precision registers and a fixed number of high precision registers, a selected number of the fixed number of low precision registers forming a spill pad, a selected number of the fixed number of high precision registers forming a spill slot, the computer system comprising:

  • a compiler system resident in said computer system having a front end compiler, a code optimizer and a back end code generator, whereinsaid code optimizer is configured to insert instructions in the target program to spill the low precision registers to the high precision registers through the spill pad and the spill slot.

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