Apparatus for enhancing sensitivity in compressive receivers and method for the same

• US 5,901,348 A
• Filed: 01/10/1997
• Issued: 05/04/1999
• Est. Priority Date: 01/10/1997
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: AIL Systems, Inc. (ITT, Inc.)
• Inventors: Burke, Peter J., Bang, William R., Levy, Joseph S.
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US08/782,545
• Time in Patent Office: 844 Days
• Field of Search: 348/725, 348/731, 348/384, 348/390, 375/240, 455/254, 455/296, 455/303, 455/305, 455/72, 455/226.1, 455/161.1, 455/161.2, 455/280, 455/338, 455/146, 455/147
• US Class Current: 455/254
• CPC Class Codes: G01S 7/354 Extracting wanted echo-signals Doppler systems G01S13/50
• CPC Class Codes: H04B 1/64 Volume compression or expansion arrangements

Abstract

A continuous wave (CW) integrator is employed within a compressive receiver to improve the sensitivity of the compressive receiver to CW signals. The CW integrator circuit partitions the bandwidth of the compressive receiver into a series of contiguous bins and integrates any signals residing within these bins over many sweeps of the compressive receiver bandwidth. By sampling and integrating CW signals present in the compressive receiver bandwidth, the CW integrator circuit improves the sensitivity of the compressive receiver by a factor approximately equal to 10 log √N, where N is the number of integrations performed.

Claims

1. A continuous wave (CW) integrator circuit for improving the sensitivity of a compressive receiver, the CW integrator circuit averaging a received analog video signal generated by the compressive receiver in response to a received synchronization signal generated by the compressive receiver, the analog video signal representing signals within a bandwidth of the compressive receiver and the synchronization signal indicating that a sweep of the bandwidth has begun, the CW integrator circuit comprising:

sampling means, the sampling means receiving the analog video signal from the compressive receiver and generating a digital sampled signal representing the analog video signal in response to a received initiation signal;

adding means, the adding means comprising first and second input ports and an output port, the first input port being operatively coupled to the sampling means and receiving the digital sampled signal therefrom, the adding means generating a signal on the output port representing the sum of signals presented to each of the first and second input ports;

storage means, the storage means comprising an input port, an output port, an address port and a plurality of storage locations, each of the plurality of storage locations being individually selectable by an address signal received by the address port, each of the plurality of storage locations containing a value representing the magnitude of signals in a segment of the bandwidth of the compressive receiver, the storage means input port being operatively coupled to the output port of the adding means, the output port of the storage means being operatively coupled to the second input port of the adding means, whereby a past value contained in a selected storage location is presented to the adding means and a new value, equal to the sum of the past value and digital sampled signal, is stored into the selected storage location replacing the past value;

averaging means, the averaging means being operatively coupled to the output port of the storage means, the averaging means performing a mathematical averaging function on the value stored within of each of the storage locations in response to a received average enable signal; and

timing means, the timing means being operatively coupled to each of the compressive receiver, the sampling means, the storage means, and the averaging means, the timing means receiving the synchronization signal from the compressive receiver and generating each of the initiation signal received by the sampling means, the address signal received by the storage means and the average enable signal received by the averaging means in response to the synchronization signal, whereby the functions of sampling, adding, storing, and averaging are performed to improve the sensitivity of the compressive receiver.

2. A CW integrator circuit, as defined by claim 1, wherein the timing means further comprises:

a variable delay generator generating a delay time, the variable delay generator comprising a trigger input terminal, an address input bus, and a delayed trigger output terminal, the trigger input terminal being operatively coupled to the compressive receiver and receiving the synchronization signal therefrom, the variable delay generator regenerating the received synchronization signal on the delayed trigger output terminal after the delay time has expired, the magnitude of the delay time corresponding to an address signal on the address input bus;

a bin storage pointer, the bin storage pointer comprising a trigger input terminal, an address output bus, and an increment integration output terminal, the trigger input terminal being operatively coupled to the compressive receiver to receive the synchronization signal therefrom, the bin storage pointer generating each of the address signal presented on the address output bus and an increment integration signal presented on the increment integration output terminal in response to the received synchronization signal, the address signal being incremented for each received synchronization signal, the address output bus being electrically coupled to each of the address input bus of the variable delay generator and the address port of the storage means whereby the delay time from the variable delay generator corresponds to a selected storage location; and

an integration counter, the integration counter having an input terminal, the input terminal being operatively coupled to the increment integration output terminal of the bin storage pointer and receiving the increment integration signal therefrom, the integration counter having an output terminal operatively coupled to the averaging means, the integration counter being responsive to the increment integration signal and generating the average enable signal which is presented on the output terminal after a predetermined number of increment integration signals have been received.

3. A CW integrator circuit, as defined by claim 2, wherein the sampling means comprises an analog to digital convertor, the storage means comprises a random access memory circuit and the averaging means comprises a microprocessor.

4. A compressive receiver circuit operating over a pre-defined bandwidth, the bandwidth being further defined by a plurality of bandwidth segments, the compressive receiver circuit generating both an analog video output signal representing signals present within the bandwidth and a synchronization signal indicating the beginning of a sweep of the bandwidth, the compressive receiver circuit including a CW integrator circuit to improve the sensitivity of the compressive receiver to CW signals, the CW integrator circuit comprising:

sampling means, the sampling means receiving the analog video signal from the compressive receiver and generating a digital sampled signal representing the analog video signal in response to a received initiation signal;

adding means, the adding means comprising first and second input ports and an output port, the first input port being operatively coupled to the sampling means and receiving the digital sampled signal therefrom, the adding means generating a signal on the output port representing the sum of signals presented to each of the first and second input ports;

storage means, the storage means comprising an input port, an output port, an address port and a plurality of storage locations, each of the plurality of storage locations being individually selectable by an address signal received by the address port, each of the plurality of storage locations containing a value representing the magnitude of signals in each of the plurality of bandwidth segments of the compressive receiver, the storage means input port being operatively coupled to the output port of the adding means, the output port of the storage means being operatively coupled to the second input port of the adding means, whereby a past value contained in a selected storage location is presented to the adding means and a new value, equal to the sum of the past value and digital sampled signal, is stored into the selected storage location replacing the past value;

averaging means, the averaging means being operatively coupled to the output port of the storage means, the averaging means performing a mathematical averaging function on the value stored within of each of the storage locations in response to a received average enable signal; and

timing means, the timing means being operatively coupled to each of the compressive receiver, the sampling means, the storage means, and the averaging means, the timing means receiving the synchronization signal from the compressive receiver and generating each of the initiation signal received by the sampling means, the address signal received by the storage means and the average enable signal received by the averaging means in response to the synchronization signal, whereby the functions of sampling, adding, storing, and averaging are performed to improve the sensitivity of the compressive receiver.

5. A compressive receiver circuit, as defined by claim 4, wherein the timing means further comprises:

a variable delay generator generating a delay time, the variable delay generator comprising a trigger input terminal, an address input bus, and a delayed trigger output terminal, the trigger input terminal being operatively coupled to the compressive receiver and receiving the synchronization signal therefrom, the variable delay generator regenerating the received synchronization signal on the delayed trigger output terminal after the delay time has expired, the magnitude of the delay time corresponding to an address signal on the address input bus;

a bin storage pointer, the bin storage pointer comprising a trigger input terminal, an address output bus, and an increment integration output terminal, the trigger input terminal being operatively coupled to the compressive receiver to receive the synchronization signal therefrom, the bin storage pointer generating each of the address signal presented on the address output bus and an increment integration signal presented on the increment integration output terminal in response to the received synchronization signal, the address signal being incremented for each received synchronization signal, the address output bus being electrically coupled to each of the address input bus of the variable delay generator and the address port of the storage means whereby the delay time from the variable delay generator corresponds to a selected storage location; and

an integration counter, the integration counter having an input terminal, the input terminal being operatively coupled to the increment integration output terminal of the bin storage pointer and receiving the increment integration signal therefrom, the integration counter having an output terminal operatively coupled to the averaging means, the integration counter being responsive to the increment integration signal and generating the average enable signal which is presented on the output terminal after a predetermined number of increment integration signals have been received.

6. A compressive receiver circuit, as defined by claim 5, wherein the sampling means comprises an analog to digital convertor, the storage means comprises a random access memory circuit, and the averaging means comprises a microprocessor.

7. A method of improving the sensitivity of a compressive receiver to CW signals within a compressive receiver bandwidth, the method comprising the steps of:

a. mapping the compressive receiver bandwidth into a plurality of contiguous, discrete bins B;

b. performing an integration scan by sequentially sampling the energy in each of the bins, thereby generating samples for each bin, and storing each of the samples;

c. performing additional integration scans and accumulating the samples for each bin to create accumulated bin values for each bin;

d. averaging the accumulated bin values for each bin after a predetermined number of integration scans have been completed; and

e. evaluating the averaged bin values from step d) to determine whether a CW signal is present within a bin.

8. A method as defined by claim 7, wherein the compressive receiver is further defined having a sweep time, the sweep time being the time required to sweep the bandwidth of the compressive receiver, and wherein the sampling of step b) comprises sampling one of the plurality of bins per sweep time of the compressive receiver.

9. A method as defined by claim 7, wherein the compressive receiver is further defined having a sweep time, the sweep time being the time required to sweep the bandwidth of the compressive receiver, and wherein step b) is completed within a time period equal to one sweep time of the compressive receiver.

10. A method as defined by claim 7, wherein the compressive receiver is further defined having a sweep time, the sweep time being the time required to sweep the bandwidth of the compressive receiver, and wherein step b) is completed within a time period being an integer multiple of the sweep time of the compressive receiver, the integer multiple being less than B.