Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures

• US 5,902,686 A
• Filed: 11/21/1996
• Issued: 05/11/1999
• Est. Priority Date: 11/21/1996
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: MCNC, Inc.
• Inventors: Mis, Joseph Daniel
• Primary Examiner(s): Zimmerman, John J.
• Application Number:
  US08/754,637
• Time in Patent Office: 901 Days
• Field of Search: 428/629, 428/647, 428/620, 428/666, 428/660, 428/601, 148/537, 148/518, 148/528, 228/180.22, 228/232, 228/254
• US Class Current: 428/629
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02315 Self-assembly processes
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05575 Plural external layers
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/11005 for aligning the bump connector, e.g. marks, spacers
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: Y10T 428/1259 : Oxide

Abstract

Method for forming a solder bump on a substrate include the steps of forming an under bump metallurgy layer on a substrate, forming a solder bump on the under bump metallurgy layer, and forming an intermetallic portion of the under bump metallurgy layer adjacent the solder bump. In particular, the solder bump has a predetermined shape and this predetermined shape is retained while forming the intermetallic portion of the under bump metallurgy layer. This predetermined shape preferably has a flat surface opposite the substrate thus providing a uniform thickness of solder during the formation of the intermetallic portion. Related structures are also disclosed.

Claims

1. A solder structure for a microelectronic substrate, said solder structure comprising:

an under bump metallurgy layer on said substrate;

a solder bump on said under bump metallurgy layer wherein said solder bump includes an oxide layer thereon opposite said under bump metallurgy layer; and

an intermetallic portion of said under bump metallurgy layer disposed between said under bump metallurgy layer and said solder bump.

2. A solder structure according to claim 1 wherein a surface of said under bump metallurgy layer opposite said substrate is wettable to said solder bump.

3. A solder structure according to claim 1 wherein said intermetallic portion of said under bump metallurgy layer comprises a constituent of said under bump metallurgy and a constituent of said solder.

4. A solder structure according to claim 1 wherein said under bump metallurgy layer comprises:

a chromium layer on said substrate;

a phased layer of chromium and copper on said chromium layer opposite said substrate; and

a copper layer on said phased layer opposite said chromium layer.

5. A solder structure according to claim 4 wherein said under bump metallurgy layer further comprises a layer of titanium between said substrate and said chromium layer.

6. A solder structure according to claim 1 wherein said solder bump includes an elongate portion and an enlarged width portion.

7. A solder structure according to claim 1 wherein said substrate includes an electrical contact having an exposed portion and wherein said solder bump electrically contacts said exposed portion of said electrical contact.

8. A method of forming a solder structure on a substrate, said method comprising the steps of:

forming an under bump metallurgy layer on said substrate;

forming a solder layer on said under bump metallurgy layer, wherein said solder layer includes an oxide layer thereon; and

forming an intermetallic portion of said under bump metallurgy layer adjacent said solder layer by heating said solder layer while maintaining said oxide layer thereon.

9. The method of claim 8 wherein said step of forming said solder layer on said under bump metallurgy layer is preceded by the step of forming a patterned mask layer on said under bump metallurgy layer that exposes a portion of said under bump metallurgy layer, and said step of forming said solder layer on said under bump metallurgy layer includes the steps of forming said solder layer on said portion of said under bump metallurgy layer and then removing said patterned mask layer.

10. The method of claim 8 wherein said step of forming an intermetallic portion is followed by the step of reflowing said solder layer to form a solder bump.

11. The method of claim 8 wherein a surface of said under bump metallurgy layer opposite said substrate is wettable to said solder layer.

12. The method of claim 8 wherein said step of forming said under bump metallurgy layer comprises the steps of:

forming a chromium layer on said substrate;

forming a phased layer of chromium and copper on said chromium layer opposite said substrate; and

forming a copper layer on said phased layer opposite said chromium layer.

13. The method of claim 12 wherein said step of forming said chromium layer is preceded by the step of forming a titanium layer on said substrate.

14. The method of claim 8 wherein said solder layer includes an elongate portion and an enlarged width portion.

15. The method of claim 8 wherein said solder layer has a flat surface opposite said substrate.

16. The method claim 8 wherein said intermetallic portion comprises a constituent of said under bump metallurgy layer and a constituent of said solder layer.

17. The method of claim 8 wherein said heating of said solder layer during said step of forming an intermetallic portion comprises heating said solder layer above the liquidus temperature of said solder layer for a period of time sufficient for said solder layer to react with said under bump metallurgy layer.

18. The method of claim 8 wherein said step of forming said intermetallic portion is followed by the steps of reducing said oxide layer and reflowing said solder layer to form a solder bump.

19. A method of forming a solder structure on a substrate, said method comprising the steps of:

forming an under bump metallurgy layer on said substrate, wherein said under bump metallurgy layer is wettable to solder;

forming a solder bump on a portion of said under bump metallurgy layer, wherein said solder bump includes an oxide layer thereon; and

forming an intermetallic portion of said under bump metallurgy layer adjacent said solder bump by heating said solder bump above its liquidus temperature while maintaining said oxide layer on said solder bump.

20. The method of claim 19 wherein said step of forming said under bump metallurgy layer comprises the steps of:

forming a chromium layer on said substrate;

forming a phased layer of chromium and copper on said chromium layer opposite said substrate; and

forming a copper layer on said phased layer opposite said chromium layer.

21. The method of claim 20 wherein said step of forming said chromium layer is preceded by the step of forming a titanium layer on said substrate.

22. The method of claim 19 wherein said solder bump includes an elongate portion and an enlarged width portion.

23. The method of claim 19 wherein said step of forming said intermetallic portion is followed by the steps of reducing said oxide layer and heating said solder bump above a liquidous temperature of said solder bump.