Low distortion level shifter

• US 5,903,142 A
• Filed: 06/27/1997
• Issued: 05/11/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mann, Eric N.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/883,971
• Time in Patent Office: 683 Days
• Field of Search: 323/311, 323/312, 323/313, 323/316, 323/317, 323/222, 363/59, 363/60, 363/95, 363/98, 326/80
• US Class Current: 323/313
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A circuit for generating an output signal in response to an input signal that propagates over devices operating at various supply voltages. The circuit generally comprises a first device operating in a first voltage, a second device operating in a second voltage and a clamp device coupled to each of the first and second devices. The clamp device generally operates at the second supply voltage, which may cause the output signal to be propagated through the circuit with a minimum distortion.

Claims

1. A circuit comprising:

a first device configured to operate at a first supply voltage and generate a first output operating at said first supply voltage;

a second device configured to generate a second output in response to said first output, wherein said second device operates at a second supply voltage different from said first supply voltage; and

a clamp device coupled to each of said first and second devices, wherein said clamp device operates at least at said second supply voltage.

2. The circuit according to claim 1 wherein said first supply voltage is at least 3.3 volts and said second supply voltage is no more than 2.5 volts.

3. The circuit according to claim 1 further comprising:

a logic circuit configured to provide said input; and

an output driver configured to receive said output.

4. The circuit according to claim 3 further comprising a pad driver circuit configure to receive said input and to present two or more pad outputs.

5. A circuit comprising:

means for generating a first output in response to an input, wherein said generating means operates at a first supply voltage;

means for generating the second output in response to said first output, wherein said second generating means operates at a second supply voltage; and

clamping means coupled to each of said first and second generating means, wherein said clamping means operates at said second supply voltage.

6. The circuit according to claim 5 wherein said first supply voltage comprises a 3.3 volts supply said second supply voltage comprises a 2.5 volt supply.

7. The circuit according to claim 5 further comprising:

logic means for generating said input; and

output means for receiving said output.

8. The circuit according to claim 7 further comprising a pad driver circuit for generating two or more pad outputs in response to said input.

9. A method for reducing the distortion of a waveform comprising:

generating a first output operating at a first supply voltage in response to an input;

generating a second output operating at a second supply voltage in response to said first output; and

clamping each of said first and second outputs, wherein said clamping operates at least at said second supply voltage.