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Clock circuit for generating a high resolution output from a low resolution clock

  • US 5,903,176 A
  • Filed: 09/04/1996
  • Issued: 05/11/1999
  • Est. Priority Date: 09/04/1996
  • Status: Expired due to Term
First Claim
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1. A high resolution clock circuit comprising:

  • a clock generating a timing frequency signal;

    a clock distribution circuit connected to said clock and having a plurality of outputs for producing a plurality of output signals therefrom;

    a plurality of delay lines, each said delay line being coupled to one of said plurality of outputs of said clock distribution circuit to receive one of the signals therefrom and each said delay line having a different signal delay from each of the other said delay lines, said delay lines outputting delayed versions of the received signals;

    a first latching circuit having each of said plurality of delay lines coupled thereto to thereby latch the signals received from said plurality of delay lines;

    a second latching circuit;

    a shift register coupled to said clock for receiving said timing frequency signal, said shift register having a plurality of outputs coupled to said second latching circuit; and

    a conversion circuit connected to said first and second latching circuits to convert signals from said first and second latching circuits into output clock signals of a higher resolution than that of said timing frequency signal.

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