Clock circuit for generating a high resolution output from a low resolution clock

• US 5,903,176 A
• Filed: 09/04/1996
• Issued: 05/11/1999
• Est. Priority Date: 09/04/1996
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Litton Systems Incorporated (Northrop Grumman Corporation)
• Inventors: Westgate, Wayne F.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/707,435
• Time in Patent Office: 979 Days
• Field of Search: 327/291-295, 327/256-258, 331/1 A, 331/57
• US Class Current: 327/295
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means
• CPC Class Codes: G04F 10/06 by measuring phase G04F10/005 takes precedence

Abstract

A high resolution clock circuit apparatus and a method of generating a high resolution clock output from a lower resolution clock input utilizes conventional technology. A standard clock generates a clock frequency which is divided by a flip-flop circuit and is applied to a low skew differential clock driver which distributes the clock into a plurality of separate outputs, each output is applied to a different length delay line. The output of each delay line is applied to a latching circuit, such as a low power octal ECL/TTL bidirectional translator. Each of the plurality of delay lines is sampled and a time word is latched when a time measurement is to be made. In this event, a control signal toggles from low to high which latches a digital word representing that subnanosecond interval of time. A shift register also receives the input clock frequency and includes a feedback loop and is applied to the latch circuit. The output of the two latches are input into a PROM used to convert the input code into a binary coded decimal.

Claims

1. A high resolution clock circuit comprising:

a clock generating a timing frequency signal;

a clock distribution circuit connected to said clock and having a plurality of outputs for producing a plurality of output signals therefrom;

a plurality of delay lines, each said delay line being coupled to one of said plurality of outputs of said clock distribution circuit to receive one of the signals therefrom and each said delay line having a different signal delay from each of the other said delay lines, said delay lines outputting delayed versions of the received signals;

a first latching circuit having each of said plurality of delay lines coupled thereto to thereby latch the signals received from said plurality of delay lines;

a second latching circuit;

a shift register coupled to said clock for receiving said timing frequency signal, said shift register having a plurality of outputs coupled to said second latching circuit; and

a conversion circuit connected to said first and second latching circuits to convert signals from said first and second latching circuits into output clock signals of a higher resolution than that of said timing frequency signal.

2. A high resolution clock circuit in accordance with claim 1 in which each delay line terminates in about 50 ohm resistance.

3. A high resolution clock circuit in accordance with claim 2 in which each delay line is an analog delay line.

4. A high resolution clock circuit in accordance with claim 1 in which said clock includes a frequency dividing circuit reducing the frequency of clock generated frequency signal.

5. A high resolution clock circuit in accordance with claim 1 in which each delay line is a coaxial cable delay line of a different length from the other delay lines.

6. A high resolution clock circuit in accordance with claim 1 in which said clock produces a 200 MHz clock input.

7. A high resolution clock circuit in accordance with claim 4 in which said frequency dividing circuit is a flip flop circuit.

8. A high resolution clock circuit in accordance with claim 1 in which said shift register has a feed back loop.

9. A high resolution clock circuit in accordance with claim 1 including a PROM coupled to the outputs from said first latching circuit to convert the signals received from said first latching circuit into binary coded decimal signals.