Voltage generating apparatus
First Claim
1. A D/A converter comprising:
- a plurality of conversion capacitors having capacitance values defined by factors depending on input bits, each of the conversion capacitors having a first end and a second end, the first end of each of the conversion capacitors being maintained at a fixed voltage;
a coupling capacitor having a first end and a second end, the first end of the coupling capacitor being maintained at a fixed voltage; and
a plurality of switches having a common node and disposed between the second end of each of the conversion capacitors and the second end of said coupling capacitor, each of the switches being opened or closed in accordance with said input bits;
wherein an analog voltage corresponding to a digital input value is obtained between the second end of said coupling capacitor and the common node of said switches, such that the designed capacitance values of said plurality of conversion capacitors satisfies equation (1) described below;
space="preserve" listing-type="equation">Coj-dCj>
Σ
.sub.(i<
j) (Coi+dCi) (for all j) (1)whereCi;
ith conversion capacitance,Coi;
designed value of the ith conversion capacitance,dCi;
dispersion of the ith conversion capacitance,Cj;
jth conversion capacitance,Coj;
designed value of the jth conversion capacitance,dCj;
dispersion of the jth conversion capacitance,Σ
.sub.(i<
j) ;
sum for all i smaller than j, andfor all j;
indicating that the equation should be satisfied for all j.
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Accused Products
Abstract
The invention provides a method and apparatus for generating a precise and stable voltage at a high speed. More specifically, there is provided a D/A converter constructed using capacitors having capacitance values which are properly deviated from binary-weighted (2n) capacitance values. This D/A converter has the feature that even if the ratios among a plurality of actual capacitances having weighted values are different from the designed values to an extreme degree, the capacitance value of the jth capacitor is always greater than the sum of the capacitance values of the first through (j-1)th capacitors. This ensures that an unwanted reverse change in the output signal of the D/A converter is prevented from occurring. Furthermore, this technique of the invention can be accomplished without having to use an additional circuit such as a compensation circuit, and therefore this technique is easy and inexpensive.
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Citations
81 Claims
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1. A D/A converter comprising:
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a plurality of conversion capacitors having capacitance values defined by factors depending on input bits, each of the conversion capacitors having a first end and a second end, the first end of each of the conversion capacitors being maintained at a fixed voltage; a coupling capacitor having a first end and a second end, the first end of the coupling capacitor being maintained at a fixed voltage; and a plurality of switches having a common node and disposed between the second end of each of the conversion capacitors and the second end of said coupling capacitor, each of the switches being opened or closed in accordance with said input bits; wherein an analog voltage corresponding to a digital input value is obtained between the second end of said coupling capacitor and the common node of said switches, such that the designed capacitance values of said plurality of conversion capacitors satisfies equation (1) described below;
space="preserve" listing-type="equation">Coj-dCj>
Σ
.sub.(i<
j) (Coi+dCi) (for all j) (1)where Ci;
ith conversion capacitance,Coi;
designed value of the ith conversion capacitance,dCi;
dispersion of the ith conversion capacitance,Cj;
jth conversion capacitance,Coj;
designed value of the jth conversion capacitance,dCj;
dispersion of the jth conversion capacitance,Σ
.sub.(i<
j) ;
sum for all i smaller than j, andfor all j;
indicating that the equation should be satisfied for all j. - View Dependent Claims (2, 3, 4, 5, 8, 9, 10)
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6. A D/A converter comprising:
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a plurality of conversion capacitors having capacitance values defined by factors depending on input bits, each of the conversion capacitors having a first end and a second end, the first end of each of the conversion capacitors being maintained at a fixed voltage; a coupling capacitor having a first end and a second end, the first end of the coupling capacitor being maintained at a fixed voltage; and a plurality of switches having a common node and disposed between the second end of each of the conversion capacitors and the second end of said coupling capacitor, each of the switches being opened or closed in accordance with said input bits; wherein an analog voltage corresponding to a digital input value is obtained between the second end of said coupling capacitor and the common node of said switches, such that the designed capacitance values of said plurality of conversion capacitors satisfies equation (2) described below;
##EQU2## where Cs;
coupling capacitance,Vc;
voltage at the other end of the coupling capacitor before the switch is closed,Vo;
voltage at the other end of the conversion capacitors before the switch is closed,Coi;
designed value of the ith conversion capacitance,dCi;
dispersion of the ith conversion capacitance,Coj;
designed value of the jth conversion capacitance,dCj;
dispersion of the jth conversion capacitance,Vth;
maximum change (visually recognizable threshold value) in the output voltage of the D/A converter, which cannot be recognized by human eyes when an image is displayed in such a manner that the brightness of the image corresponds to the output voltage of the D/A converter,Σ
.sub.(i<
j) ;
sum for all i smaller than j,for all j;
indicating that the equation should be satisfied for all j. - View Dependent Claims (7)
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11. A D/A converter for converting a digital signal that includes n (integer) bits Di (i=1, 2, . . . , n) to an analog output signal Vout, said D/A converter comprising:
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n conversion capacitors Cxi corresponding to the respective bits Di of said digital signal and having electrodes; at least one conversion selection line along which n different voltages Vxi corresponding to the respective bits Di of said digital signal; an output line via which said analog output signal Vout is output; and a first reference voltage line connected to one electrode of each of the n capacitors Cxi and maintained at a voltage Vs1;
whereinother electrodes of the conversion capacitors Cxi corresponding to the bits Di of the digital signal in an on-state are connected to said conversion selection line so that conversion charges corresponding to differences between the voltages Vxi and Vs1 are stored in the corresponding conversion capacitors Cxi; the other electrodes of the conversion capacitors Cxi corresponding to the bits Di of the digital signal in an off-state are connected to a predetermined line; and after said conversion charges have been stored, the other electrodes are electrically disconnected from at least one of said conversion selection line and said predetermined line and then connected to said output line so that said conversion charges are combined and an analog output signal Vout corresponding to the total charge is output. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 40, 41, 42, 43, 44, 45, 46)
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33. A D/A converter for converting a digital signal that includes n (integer) bits Di (i=1, 2, . . . , n) to an analog output signal Vout, said D/A converter comprising:
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n conversion capacitors Cxi corresponding to the respective bits Di of said digital signal; and at least one conversion selection line along which different voltages Vxi are supplied;
whereinsaid voltages Vxi and the capacitance values of said conversion capacitors Cxi are set so that conversion charges corresponding to the respective bit values Di of said digital signal are stored in corresponding conversion capacitors Cxi and so that an analog output signal Vout corresponding to at least one of the total value and the sum of said conversion charges is output.
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34. A D/A conversion method for converting a digital signal that includes n (integer) bits Di (i=1, 2, . . . , n) to an analog output signal Vout, said method comprising the steps of:
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storing, for each on-state bit of said digital signal, a conversion charge into the corresponding one of n conversion capacitors Cxi in accordance with the corresponding voltage of n different voltages Vi, while maintaining the conversion charges stored in said conversion capacitors Cxi corresponding to the off-state bits Di of said digital signal constant regardless of the bits Di; and determining a sum of said conversion charges and supplying an analog output signal Vout corresponding to a total charge equal to the sum of said conversion charges. - View Dependent Claims (35, 36, 37, 38)
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39. A D/A conversion method for converting a digital signal that includes n (integer) bits Di (i=1, 2, . . . , n) to an analog output signal Vout, said method comprising the steps of:
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selecting, for each on-state bit Di of said digital signal, one voltage from a plurality of different voltages Vxi in accordance with each on-state bit Di of said digital signal, and storing a corresponding conversion charge into the corresponding one of the n conversion capacitors Cxi, while maintaining the conversion charges stored in said conversion capacitors Cxi corresponding to the off-state bits Di of said digital signal constant regardless of the bits Di; and determining a sum of said conversion charges and supplying an analog output signal Vout corresponding to a total charge equal to the sum of said conversion charges.
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47. A method of precharging signal lines of an active matrix type of display device, said display device including a plurality of scanning lines, a plurality of signal lines, and switching elements connected to the respective scanning lines and the respective signal lines, said precharging being performed before supplying an image signal to said signal lines, said method comprising the steps of:
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preparing switches such that each signal line has its own switch that selects one of different precharging DC voltages and selectively connects the signal line to the selected precharging DC voltage; and operating said switches so that said signal lines are connected to one of said precharging DC voltages, thereby precharging said signal line into the same polarity as the polarity of said image signal relative to a center voltage of its amplitude. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72)
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73. A method of precharging signal lines of an active matrix type of display device, said display device including a plurality of scanning lines;
- a plurality of signal lines;
switching elements connected to the respective scanning lines and the respective signal lines, said precharging being performed before supplying an image signal to said signal lines, said method comprising the steps of;preparing a first precharging voltage line, a second precharging voltage line having a voltage different from that of said first precharging voltage line, and switches such that each signal line has its own switch that connects the signal line to at least one of said first precharging voltage line and said second precharging voltage line; and operating said switches so that said signal lines are connected to at least one of said first precharging voltage line and said second precharging voltage line thereby precharging said signal lines, wherein the voltages on said first and second precharging voltage lines are periodically inverted.
- a plurality of signal lines;
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74. A circuit for precharging signal lines of an active matrix type of display device, said display device including a plurality of scanning lines;
- a plurality of signal lines;
switching elements connected to the respective scanning lines and the respective signal lines, said precharging being performed before supplying an image signal to said signal lines, said circuit comprising;a first precharging voltage line; a second precharging voltage line having a voltage different from that of said first precharging voltage line; switches for selectively connecting said signal lines to at least one of said first precharging voltage line and said second precharging voltage line; and a switching controller for controlling the on/off operation of said switches. - View Dependent Claims (78, 79, 80, 81)
- a plurality of signal lines;
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75. A circuit for precharging signal lines of a liquid crystal display device, said display device including a plurality of scanning lines;
- a plurality of signal lines;
switching elements disposed at respective intersections between said scanning lines and said signal lines for controlling the electrical connections between a liquid crystal and the signal lines, said precharging being performed before supplying an image signal to said signal lines, said circuit comprising;a first precharging voltage line; a second precharging voltage line having a voltage different from that of said first precharging voltage line; first switches provided such that each signal line has its own first switch for switching connection/disconnection between said signal line and said first precharging voltage line; second switches provided such that each signal line has its own second switch for switching connection/disconnection between said signal line and said second precharging voltage line; and a switching controller for controlling the on/off operation of said first and second switches. - View Dependent Claims (76, 77)
- a plurality of signal lines;
Specification