Electrostatic discharge protecting circuit having a plurality of current paths in both directions

• US 5,903,420 A
• Filed: 11/03/1997
• Issued: 05/11/1999
• Est. Priority Date: 11/02/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ham, Seog-Heon
• Primary Examiner(s): Leja, Ronald W.
• Application Number:
  US08/963,238
• Time in Patent Office: 554 Days
• Field of Search: 361/18, 361/56, 361/91, 361/111, 361/119, 257/107, 257/121, 257/122, 257/124, 257/126, 257/133, 257/146, 257/355
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements

Abstract

An electrostatic discharge (ESD) protecting circuit for effectively discharging an overcurrent applied to a semiconductor circuit device, by providing a plurality of current paths. The ESD protecting circuit comprises a first discharging current path for discharging an overcurrent from the I/O pad to a first power supply, a second discharging current path for discharging the overcurrent from the I/O pad to a second power supply providing power for the internal circuit and a third discharging current path formed between the first power supply and the second power supply.

Claims

1. An electrostatic discharge (ESD) protecting circuit formed between an input/output (I/O) pad and an internal circuit of a semiconductor device, said ESD protecting circuit comprising:

an N-well region formed on a semiconductor substrate;

a P-well region formed on said semiconductor substrate, being adjacent to said N-well region;

a first impurity region being in contact with both said P-well region and said N-well region;

a first transistor, one terminal of which is coupled to a first power supply and another of which is coupled to said I/O pad, for discharging an overcurrent from said I/O pad;

a second transistor, one terminal of which is coupled to a second power supply and another of which is coupled to said I/O pad;

a second impurity region formed on said P-well region to be electrically coupled to said first power supply, being coupled to one terminal of said first transistor;

a third impurity region formed on said N-well region to be electrically coupled to said second power supply, being coupled to one terminal of said second transistor;

a first insulating layer for isolating said first impurity region from said first transistor; and

a second insulating layer for isolating said first impurity region from said second transistor.

2. The ESD protecting circuit in accordance with claim 1, wherein said second and third impurity regions are p⁺ and n⁺ -type impurity regions, respectively.

3. The ESD protecting circuit in accordance with claim 2, wherein said first and second transistors are N-channel and P-channel MOSFETs, respectively, wherein said gate electrode of said N-channel MOSFET is coupled to said first power supply and wherein said gate electrode of said P-channel MOSFET is coupled to said second power supply.

4. The ESD protecting circuit in accordance with claim 3, wherein said first impurity region is a p⁺ or n⁺ -type impurity region.

5. An electrostatic discharge (ESD) protecting circuit formed between an input/output (I/O) pad and an internal circuit of a semiconductor device, said ESD protecting circuit comprising:

an N-well region formed on a semiconductor substrate;

a P-well region formed on said semiconductor substrate, being adjacent to said N-well region;

a first impurity region being in contact with both said P-well region and said N-well region;

a first transistor, one terminal of which is coupled to a first power supply and another of which is coupled to said I/O pad, for discharging an overcurrent from said I/O pad in response to a voltage applied to a gate electrode thereof;

a second transistor, one terminal of which is coupled to a second power supply and another of which is coupled to said I/O pad, for discharging said overcurrent in response to a voltage applied to a gate electrode thereof;

a second impurity region formed on said P-well region to be electrically coupled to said first power supply, being coupled to one terminal of said first transistor; and

a third impurity region formed on said N-well region to be electrically coupled to said second power supply, being coupled to one terminal of said second transistor.

6. The ESD protecting circuit in accordance with claim 5, wherein said second and third impurity regions are p⁺ and n⁺ -type impurity regions, respectively.

7. The ESD protecting circuit in accordance with claim 6, wherein said first impurity region is a p⁺ or n⁺ -type impurity region.

8. The ESD protecting circuit in accordance with claim 5, wherein said first and second transistors are NPN and PNP lateral Bipolar Transistors or NMOSFET and PMOSFET.