Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows

• US 5,903,461 A
• Filed: 05/23/1997
• Issued: 05/11/1999
• Est. Priority Date: 04/19/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, Koford, James S., Boyle, Douglas B., Rostoker, Michael D., Jones, Edwin R.
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/862,791
• Time in Patent Office: 718 Days
• Field of Search: 364/468.28, 364/488-491, 395/10, 395/13, 395/902, 395/904, 395/919, 395/921, 395/920
• US Class Current: 700/121
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

Claims

1. A method of cell placement for an integrated circuit chip, comprising the steps of:

(a) computing centroids for a plurality of cells of said placement as a first predetermined function of locations of cells to which said cells are connected respectively;

(b) computing first distances from current locations of said cells to said centroids respectively;

(c) computing second distances as a second predetermined function of said first distances respectively;

(d) moving said cells from said current locations toward said centroids by said second distances respectively;

(e) defining a movable window that delineates subsets of cells of said placement; and

(f) individually performing a predetermined placement improvement operation on said subsets.

2. A method as in claim 1, in which:

steps (a) to (d) allow a location to contain more than one cell; and

the method further comprises the step after step (d), of;

(g) distributing the cells into respective locations such that each location is occupied by one cell.

3. A method as in claim 1, in which:

steps (a) to (d) allow more than one cell to be moved to a single location, and allow locations to have no cells thereat; and

the method further comprises the step, performed after step (d), of;

(g) distributing the cells into respective locations such that each location is occupied by one cell.

4. A method as in claim 3, in which step (g) comprises distributing said cells into locations that are substantially closest to locations that said cells occupied after performing step (d).

5. A method as in claim 1, in which said predetermined placement improvement operation comprises a genetic algorithm.

6. A method as in claim 1, in which said predetermined placement improvement operation comprises genetic mutation.

7. A method as in claim 1, in which said predetermined placement improvement operation comprises simulated annealing.

8. A method as in claim 1, in which step (a) comprises selecting said plurality of cells randomly.

9. A method as in claim 1, in which step (a) comprises selecting said plurality of cells in accordance with a predetermined fitness criterion.

10. A method as in claim 1, in which step (a) comprises selecting said plurality of cells in a predetermined order.

11. A method as in claim 1, in which step (a) comprises selecting said plurality of cells in accordance with said locations of cells to which said plurality of cells are connected respectively.

12. A method as in claim 1, in which steps (a) to (d) are performed sequentially on said plurality of cells.

13. A method as in claim 1, in which steps (a) to (d) are performed in parallel on said plurality of cells.

14. A method as in claim 1, further comprising the steps, performed after step (d) of:

(e) selecting a new plurality of cells; and

(f) repeating steps (a) to (d) for said new plurality of cells.

15. A method as in claim 14, further comprising the step, performed after step (f), of:

(g) repeating steps (e) and (f) a predetermined number of times.

16. A method as in claim 14, further comprising the steps, performed after step (f), of:

(g) measuring said fitness of said placement; and

(h) repeating steps (e) and (f) if said fitness is below a predetermined value.

17. A method as in claim 16, in which step (g) comprises measuring said fitness as a predetermined function of cell interconnect congestion.

18. A method as in claim 14, further comprising the steps, performed after step (f) of:

(g) measuring said fitness of said placement; and

(h) repeating steps (e) and (f) if said fitness has changed by more than a predetermined value.

19. A method as in claim 1, in which:

step (e) comprises moving said window to a plurality of predetermined locations in said placement; and

step (f) comprises successively performing said improvement operation to said subsets that are delineated by said window in said locations respectively.

20. A method as in claim 19, in which step (e) comprises selecting said locations such that each entity is delineated by said window and said improvement operation is performed thereon at least once.

21. A method as in claim 19, in which step (e) comprises dimensioning said window and selecting said locations such that adjacent subsets partially overlap.

22. A method as in claim 19, further comprising the steps of:

(g) successively moving a second window having a different size than said window to a plurality of predetermined second locations in said placement; and

(h) successively performing said improvement operation on second subsets that are delineated by said second window in said second locations respectively.

23. A method as in claim 22, in which:

steps (e) and (g) comprise dimensioning said window and said second window and selecting said locations and said second locations such that said subsets and said second subsets partially overlap.

24. A method as in claim 23, in which:

step (e) comprises dimensioning said window and selecting said locations such that said subsets are contiguous; and

step (g) comprises dimensioning said second window and selecting said second locations such that said second subsets are contiguous.

25. A method as in claim 19, in which:

step (e) further comprises defining a second window that is integrally movable with and circumscribes said window such that a border area is defined between peripheries of said window and said second window; and

step (f) comprises performing said improvement operation such that misplaced cells are allowed to move from said window into said border area.

26. A method as in claim 25, further comprising the step of:

(g) computing and moving said misplaced cells to new locations respectively in accordance with a predetermined function.

27. A method as in claim 26, in which step (g) comprises computing each new location as a centroid of a net of cells to which a respective misplaced cell is connected.

28. A method as in claim 25, further comprising the step of:

(g) computing new locations for said misplaced cells in accordance with a predetermined function; and

(h) attempting to move said misplaced cells to said new locations respectively.

29. A method as in claim 28, in which step (g) comprises computing each new location as a centroid of a net of cells to which a respective misplaced cell is connected.

30. A method as in claim 28, further comprising the step of:

(i) controlling step (f) to exclude a misplaced cell from a subsequent improvement operation if an attempt to move said misplaced cell to a new location is unsuccessful.

31. A method as in claim 30, in which step (i) comprises determining that an attempt to move a misplaced cell to a new location is unsuccessful if said new location is already occupied by another cell.

32. A method as in claim 30, in which step (g) comprises computing a new location as a centroid of a net of cells to which a respective misplaced cell is connected, comprising any of said misplaced cells that are included in said net in said new locations thereof.

33. A method as in claim 1, further comprising the steps of:

(g) movably defining a second window that does not overlap said window and delineates second subsets of cells of said placement; and

(h) independently performing said improvement operation on said subsets and said second subsets respectively.

34. A method as in claim 33, in which steps (e) and (g) comprise moving said window and said second window integrally.

35. A method of cell placement for an integrated circuit chip, comprising the steps of:

(a) performing a chaotic placement improvement operation on said placement; and

(b) performing a predetermined fitness improvement operation on said placement within at least one moving window.

36. A method as in claim 35, in which step (b) comprises performing said predetermined placement improvement operation as including a genetic algorithm.

37. A method as in claim 35, in which step (b) comprises performing said predetermined placement improvement operation as including genetic mutation.

38. A method as in claim 35, in which step (b) comprises performing said predetermined placement improvement operation as including simulated annealing.

39. A method as in claim 35, in which:

step (a) comprises concurrently performing said chaotic placement operation on a plurality of said cells in parallel; and

step (b) comprises concurrently performing said predetermined placement improvement operation within a plurality of moving windows in parallel.

40. A method of cell placement for an integrated circuit chip, comprising the steps of:

performing a chaotic cell placement of said cells using the attractive properties and repelling properties between said cells;

distributing cells occupying the same location as other cells into respective locations such that each location is occupied by one cell;

defining a movable window delineating subsets of cells of said placement; and

performing a predetermined placement improvement operation on said subsets defined by the movable window.