Integrated circuit for processing digital signal

• US 5,903,481 A
• Filed: 05/06/1996
• Issued: 05/11/1999
• Est. Priority Date: 09/09/1994
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kondo, Tetsujiro, Horishi, Takashi
• Primary Examiner(s): Elmore, Reba I.
• Assistant Examiner(s): Marc, McDieunel, Marc, McDieunel
• Application Number:
  US08/640,747
• Time in Patent Office: 1,100 Days
• Field of Search: 364/724.01, 364/231, 364/231.2, 364/231.3, 364/232.2, 364/232.7, 364/232.8, 364/232.9, 364/223, 364/700, 364/707, 364/926, 257/113, 257/114, 257/116, 257/43, 257/44, 257/265, 257/263, 257/272, 257/338, 257/368, 326/15, 324/674, 324/681, 324/707, 396/127, 701/114, 370/60.1
• US Class Current: 708/313
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

An integrated circuit formed on a single chip, such as a large-scale integration (LSI) chip, which enables a plurality of digital signal processing functions to be performed. A desired digital signal processing function may be selected from among the plurality of available processing functions by the use of a control signal or signals supplied from outside the LSI chip. The LSI chip may include input terminals t1, t2, and t2'"'"'; output terminals t3 and t4; and a control signal input terminal t5. Additionally, the LSI chip may further include class sorting circuits, delay and switching circuits, switching circuits, coefficient memories, filter operating circuits, a line delay circuit, and a product sum operating circuit.

Claims

1. An integrated circuit for processing a digital signal, in which a plurality of circuit groups and a number of selecting devices which can switch at least two states are provided in a single integrated circuit and said number of selecting devices are selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside the integrated circuit,

wherein when said number of selecting devices provided in said single integrated circuit select a first selection state, at least a part of said plurality of circuit groups is set to a first connecting state and is enabled to perform a first signal processing function in said first connection state and, when said number of selecting devices provided in said single integrated circuit select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state.

2. An integrated circuit for processing a digital signal according to claim 1, in which the first signal processing function involves changing a resolution of said digital signal and the second signal processing function involves noise reduction.

4. An integrated circuit for processing a digital signal according to claim 2,

characterized in that said plurality of circuit groups comprise:

first and second filter operating means;

means for supplying tap outputs to said first and second filter operating means;

means for sorting a class of pixel data which is predicted by said first and second filter operating means, respectively; and

a memory for giving filter coefficients to said first and second filter operating means in correspondence to class information from said class sorting means, respectively.

5. An integrated circuit for processing a digital signal according to claim 4, in which one of the selection states is one of a one-dimensional digital filter, a 2-dimensional digital filter, and a 3-dimensional digital filter.

6. An integrated circuit for processing a digital signal according to claim 4,

characterized in that as a tap output which is given to one of said first and second filter operating means, it is enabled to switch at least a one-dimensional tap output and a two-dimensional tap output.

7. An integrated circuit for processing a digital signal according to claim 4,

characterized in that as a class sorting for generating a coefficient which is given to one of said first and second filter operating means, it is enabled to switch at least a one-dimensional class sorting and a two-dimensional class sorting.

8. An integrated circuit for processing a digital signal according to claim 2, in which the first signal processing function involves chancing a resolution of said digital signal and the second signal processing function involves noise reduction.

3. An integrated circuit for processing a digital signal, in which a plurality of circuit groups and a number of selecting devices which can switch at least two states are provided in a single integrated circuit and said number of selecting devices are selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside the integrated circuit,

wherein when said number of selecting devices provided in said single integrated circuit select a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and when said number of selecting devices provided in said single integrated circuit select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state, and

wherein at least a part of said plurality of circuit groups is set to have a circuit function which is different in accordance with the selection state of said number of selecting devices, thereby switching the signal processing functions of the whole integrated circuit.

9. An integrated circuit for processing a digital signal having a plurality of circuit groups and a number of selecting devices for selecting at least two states which are provided in a single integrated circuit formed on a single chip, said number of selecting devices being selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside said chip such that when said number of selecting devices provided in said single integrated circuit formed on said single chip select a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and, when said number of selecting devices provided in said single integrated circuit formed on said single chip select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said first connection state.

10. An integrated circuit for processing a digital signal having a plurality of circuit groups and a number of selecting devices for selecting at least two states which are provided in a single integrated circuit formed on a single chip, said number of selecting devices being selectively controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside said chip such that when said number of selecting devices provided in said single integrated circuit formed on said single chip select a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and when said number of selecting devices provided in said single integrated circuit formed on said single chip select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said first connection state, and in which at least a part of said plurality of circuit groups has a circuit function which is set in accordance with the selection state of said number of selecting devices so as to set the signal processing functions of the entire integrated circuit.