Semiconductor device and memory system

• US 5,903,495 A
• Filed: 03/17/1997
• Issued: 05/11/1999
• Est. Priority Date: 03/18/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken, Tanaka, Tomoharu
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US08/819,484
• Time in Patent Office: 785 Days
• Field of Search: 365/185.03, 365/185.21, 365/185.22, 365/185.24, 365/185.28
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.

Claims

1. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n),

wherein said memory cells are programmed to "1," "2," . . . , "k-1," or "k," (k>

m) according to write data items input from an external device and data items held in said memory cells when said memory cells hold "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number).

3. A semiconductor memory device according to claim 1 or 2, wherein "1" is an erased state, and the threshold voltage distribution width of "2," "3," . . . , "m-1" or "m" in the memory cell is narrower than the threshold voltage distribution width of "m+1," "m+2,".

2. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein when each memory cell is programmed to a threshold voltage corresponding to "1," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number) in a first programming operation according to a write data item input from an external device, and when each memory cell is programmed to a threshold voltage corresponding to "1," "2," . . . "m-1," or "m," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "k-1" or "k" (k is a natural number greater than m) in a second programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and

a step-up value Δ

Vpp1 by which the bias increases in the first programming operation is less than a step-up value Δ

Vpp2 by which the bias increases in the second programming operation (Δ

Vpp1<

Δ

Vpp2).

4. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n),

wherein when each memory cell holds "1," "2," . . . , "2^m-1 -1" or "2^m-1 " (m is a natural number satisfying n=2^m), the memory cell comes to store "1," "2," . . . , "2^m -1" or "2^m " according to a write data item input from an external device and a data item held in the memory cell.

7. A semiconductor memory device according to claim 4, or 5, wherein "1" is an erased state, and the threshold voltage distribution width of "2," "3," . . . , "2^m-1 -1" or "2^m-1 " in the memory cell is narrower than the threshold voltage distribution width of "2^m-1 +1," "2^m-1 +2" . . . , "2^m-1 " or "2^m " in the memory cell.

5. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein each memory cell has a threshold voltage changed to store "1" or "2" in a first programming operation according to a write data item input from an external device and the threshold voltage of the memory cell when the memory cell has a threshold voltage corresponding to "1", and has a threshold voltage changed to "1," "2," . . . , "2^m -1" or "2^m " (m is a natural number satisfying n=2^m) in the m-th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell when the memory cell has a threshold voltage corresponding to "1," "2," . . . , "2^m-1 -1" or "2^m-1,"; and

a step-up value Δ

Vpp1 by which the bias increases in the first programming operation is less than a step-up value Δ

Vppm by which the bias increases in the m-th programming operation (Δ

Vpp1<

Δ

Vppm).

6. A semiconductor memory device according to claim 5, wherein the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "2^m-1 +1," "2^m-1 +2" . . . , "2^m-1 " or "2^m " in the memory cell.

8. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or greater than n),

wherein when each memory cell holds "1" or "2," the memory cell comes to store "1," "2," "3," or "4" according to a write data item input from an external device and a data item held in the memory cell.

10. A semiconductor memory device according to claim 8, wherein "1" is an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4".

9. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein when each memory cell is programmed to a threshold voltage corresponding to "1," the threshold voltage is changed to a threshold voltage corresponding to "1" or "2" in a first programming operation according to a write data item input from an external device;

when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," "3," or "4" in the second programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and

a step-up value Δ

Vpp1 by which the bias increases in the first programming operation is less than a step-up value Δ

Vpp2 by which the bias increases in the second programming operation (Δ

Vpp1<

Δ

Vpp2).

11. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n),

wherein when each memory cell holds "1," "2," . . . , "r-1" or "r" (r is 2 or a greater natural number), the memory cell comes to store "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r) according to a write data item input from an external device and a data item held in the memory cell; and

when each memory cell holds "1," "2," . . . , "s-1" or "s," the memory cell comes to store "1," "2," . . . , "t-1" or "t" (t is a natural number greater than s) according to a write data item input from an external device and a data item held in the memory cell.

13. A semiconductor memory device according to claim 11, wherein the threshold voltage distribution width of "r+1," "r+2," . . . , "s-1" or "s" in the memory cell is narrower than the threshold voltage distribution width of "s+1," "s+2," . . . , "t-1," "t."

14. A semiconductor memory device according to claim 13, wherein "1" is an erased state, and the threshold voltage distribution width of "2," . . . , "r-1" or "r" in the memory cell is narrower than the threshold voltage distribution width of "r+1," "r+2," . . . , "s-1," "s".

26. A semiconductor memory device according to claim 14, wherein "1" is an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4."

12. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein when each memory cell is programmed to a threshold voltage corresponding to "1," "2," . . . , "r-1" or "r" (r is 2 or a greater natural number), the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r) in the j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and threshold voltage of the memory cell;

when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," . . . , "s-1" or "s," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "t-1," or "t" (t is a natural number greater than s) in the (j+1)th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and

a step-up value Δ

Vppj by which the bias increases in the j-th programming operation is less than a step-up value Δ

Vpp(j+1) by which the bias increases in the (j+1)th programming operation (Δ

Vppj<

Δ

Vpp(j+1)).

15. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n),

wherein when each memory cell holds "1," "2," . . . , "2^k-1 1" or "2^k-1 " (k is 2 or a greater natural number), the memory cell comes to store "1," "2," . . . , "2^k -1" or "2^k " according to a write data item input from an external device and a data item held in the memory cell; and

when each memory cell holds "1," "2," "2^k -1" or "2^k," the memory cell comes to store "1," "2," . . . , "2^k+1 -1" or "2^k+1 " according to a write data external device and a data item held in the memory cell.

17. A semiconductor memory device according to claim 15, wherein the threshold voltage distribution width of "2^k-1 +1" or "2^k-1 +2," . . . , "2^k -1" and "2^k " in the memory cell is narrower than the threshold voltage distribution width of "2^k +1," "2^k +2," . . . , "2^k+1 -1" or "2^k+1."

18. A semiconductor memory device according to claim 15, wherein "1" is an erased state, and the threshold voltage distribution width of "1," "2," . . . , "2^k-1 -1" or "2^k-1 " in the memory cell is narrower than the threshold voltage distribution width of "2^k-1 +1," "2^k-1 +2," . . . , "2^k -1" or "2^k."

19. A semiconductor memory device according to claim 15, wherein "1" is an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3," "4," . . . , "2^k-1 -1," or "2^k-1."

16. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein when each memory cell is programmed to a threshold voltage corresponding to "1," "2," . . . , "2^k-1 -1" or "2^k-1 " (k is 2 or a greater natural number), the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "2^k -1" or "2^k " in the k-th programming operation according to a write data item input from an external device and threshold voltage of the memory cell;

when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," . . . , "2^k -1" or "2^k," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "2^k+1 -1, " or "2^k+1 " in the (k+1)th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and

a step-up value Δ

Vppk by which the bias increases in the kth programming operation is less than a step-up value Δ

Vpp(k+1) by which the bias increases in the (k+1)th programming operation (Δ

Vppk<

Δ

Vpp(k+1)).

20. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3,"and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n),

wherein during the first programming operation, each memory cell stores "1" if the input data is a first logic level and stores "2" if the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" if the input data is a 2k-1)th logic level and stores "A+2^k-1 " if the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number).

22. A semiconductor memory device according to claim 20 or 21, wherein "1" is an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "A+2^k-1."

23. A semiconductor memory device according to claim 20 or 21, wherein the threshold voltage distribution width of "A" in the memory cell is narrower than the threshold voltage distribution width of "A+2^k-1."

21. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly apply the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein during the first programming operation, each memory cell stores "1" if the input data is a first logic level and stores "2" if the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" if the input data is a (2k-1)th logic level and stores "A+2^k-1 " if the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number); and

a step-up value Δ

Vpp1 by which the bias increases in the first mode for performing the first programming operation is less than a step-up value Δ

Vppk by which the bias increases in the kth programming operation for performing the k-th programing operation (Δ

Vpp1<

Vppk).

24. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to "i" (i is a natural number equal to or less than n),

wherein during the first programming operation, each memory cell stores "1" if the input data is a first logic level and stores "2" if the input data is a second logic level;

during the second programming operation, each memory cell stores "1" if the input data is a third logic level or stores "3" if the input data is a fourth logic level in the case where the memory cell has been storing "1" during the first programming operation; and

during the second programming operation, each memory cell stores "2" if the input data is the third logic level or stores "4" if the input data is the fourth logic level in the case where the memory cell has been storing "2" during the first programming operation.

27. A semiconductor memory device according to claim 24, wherein the third threshold voltage is higher than the second threshold voltage.

28. A semiconductor memory device according to claim 27, wherein a difference between threshold voltage distributions corresponding to "3" and "4" is equal to a difference between threshold voltage distributions corresponding to "2" and "3."

29. A semiconductor memory device according to claim 27, wherein a difference between threshold voltage distributions corresponding to "3" and "4" is greater than a difference between threshold voltage distributions corresponding to "2" and "3."

30. A semiconductor memory device according to claim 24, wherein the third threshold voltage is lower than the second threshold voltage.

31. A semiconductor memory device according to claim 30, wherein a difference between threshold voltage distributions corresponding to "2" and "4" is equal to a difference between threshold voltage distributions corresponding to "2" and "3."

32. A semiconductor memory device according to claim 30, wherein a difference between threshold voltage distributions corresponding to "2" and "4" is greater than a difference between threshold voltage distributions corresponding to "2" and "3."

35. A semiconductor memory device according to claim 24, wherein the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

25. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein during the first programming operation, each memory cell stores "1" if the input data is a first logic level and stores "2" if the input data is a second logic level;

during the second programming operation, each memory cell stores "1" if the input data is a third logic level or stores "3" if the input data is a fourth logic level in the case where the memory cell has been storing "1" during the first programming operation;

during the second programming operation, each memory cell stores "2" if the input data is the third logic level or stores "4" if the input data is the fourth logic level in the case where the memory cell has been storing "2" during the first programming operation; and

a step-up value Δ

Vpp1 by which the bias increases in the first mode for performing the first programming operation is less than a step-up value Δ

Vpp2 by which the bias increase in the second programming operation for performing the second programming operation (Δ

Vpp1<

Δ

Vpp2).

36. A semiconductor memory device according to claim 25, wherein the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

33. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n),

wherein during the first programming operation, each memory cell stores "1" if the input data is a first logic level and stores "2" if the input data is a second logic level;

during the second programming operation, each memory cell stores "1" if the input data is a third logic level and according to the data item held in the memory cell, and stores "3" if the input data is a fourth logic level and according to the data item held in the memory cell, in the case where the memory cell has been storing "1" during the first programming operation; and

during the second programming operation, each memory cell stores "2" if the input data is the third logic level and according to the data item held in the memory cell, and stores "4" if the input data is the fourth logic level and according to the data item held in the memory cell, in the case where the memory cell has been storing "2" during the first programming operation.

37. A semiconductor memory device according to claim 33, wherein the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

34. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and

a data circuit for holding a write data to be written into said memory cells,

wherein each memory cell stores "1" when a first write data item held in said data circuit is at a first logic level and stores "2" when the first write data item is at a second logic level; and

after said data circuit holds a second write data item input from an external device and a data item read from each memory cell, the memory comes to store "1" when the memory cell stores "1" and said data circuit holds the second write data item of a third logic level, comes to store "3" when the memory cell stores "1" and said data circuit holds the second write data item of a fourth logic level, comes to store "2" when the memory cell stores "2" and said data circuit holds the second write data item of the third logic level, comes to store "4" when the memory cell stores "2" and said data circuit holds the second write data item of the fourth logic level.

38. A semiconductor memory device according to claim 34, wherein the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

39. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and

a data circuit for holding a write data to be written into said memory cells,

wherein when each memory cell stores "1," "2," . . . , "m-1," or "m" (m is a natural number greater than

     2), the memory cell stores "1," "2," . . . , "k-1" or "k" (k is a natural number greater than m) according to a write data item input from an external device and also a data item read from the memory cell and held in the data circuit.

41. A semiconductor memory device according to claim 39, wherein "1" is an erased state, and the threshold voltage distribution width of "2," "3,", . . . , "m-1" or "m" in the memory cell is narrower than the threshold voltage distribution width of "m+1," "m+2," . . . , "k-1" or "k".

40. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and

a data circuit for holding a write data to be written into said memory cells,

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein when each memory cell is at a threshold voltage to store "1," the memory cell is programmed to a threshold voltage to store "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number) in a first programming operation according to a write data item input from an external device and held in the data circuit;

when each memory cell is at a threshold voltage to store "1," "2," . . . , "m-1" or "m," the memory cell is programmed to a threshold voltage to store "1," "2," . . . , "k-1" or "k" (k is a natural number greater than m) in a second programming operation according to a write data input from the external device and held in the data circuit and also a data item read from the memory cell; and

a step-up value Δ

Vpp1 by which the bias increases in the first programming operation is less than a step-up value Δ

Vpp2 by which the bias increases in the second programming operation (Δ

Vpp1<

Δ

Vpp2).

42. A semiconductor memory device comprising:

n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and

a data circuit for holding a write data to be written into said memory cells,

wherein when each memory cell stores "1" or "2," the memory cell is programmed to "1," "2," "3" or "4" according to a write data item input from an external device and also a data item read from the memory cell and held in the data circuit.

44. A semiconductor memory device according to claim 42, wherein "1" is an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4."

43. A semiconductor memory device comprising:

n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n);

a data circuit for holding a write data to be written into said memory cells;

programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and

verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell,

wherein when each memory cell is at a threshold voltage to store "1," the memory cell is programmed to a threshold voltage to store "1" or "2" in a first programming operation according to a write data item input from an external device and held in the data circuit;

when each memory cell is at a threshold voltage to store "1" or "2," the memory cell is programmed to a threshold voltage to store "1," "2," "3" or "4" in a second programming operation according to a write data input from the external device and also a data item read from the memory cell and held in the data circuit; and

a step-up value Δ

Vpp1 by which the bias increases I the first programming operation is less than a step-up value Δ

Vpp2 by which the bias increases in the second programming operation (Δ

Vpp1<

Vpp2).