Floating point timer
First Claim
Patent Images
1. A floating point timer comprising:
- a floating point counter responsive to a start signal and a count signal for counting a number of occurrences of receiving the count signal since the start signal was received; and
a digital ring oscillator for periodically outputting the count signal at an oscillation period that matches the delay of the worst case path of said floating point counter.
1 Assignment
0 Petitions
Accused Products
Abstract
A floating point timer comprises a floating point counter using a reference clock signal generated by a digital ring oscillator having an oscillation period that matches the delay of the worst case path through the floating point counter. The digital ring oscillator utilizes a digital delay line which repeatedly delays a bit for the oscillation period and feedback logic to reapply the delayed bit for another oscillation. The digital delay line includes enough high-precision digital delay elements whereby the oscillation period is at least as great as that of the delay of the worst case path through the floating point counter.
24 Citations
7 Claims
-
1. A floating point timer comprising:
-
a floating point counter responsive to a start signal and a count signal for counting a number of occurrences of receiving the count signal since the start signal was received; and a digital ring oscillator for periodically outputting the count signal at an oscillation period that matches the delay of the worst case path of said floating point counter. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A floating point timer responsive to a start signal, comprising:
-
a digital delay line for delaying a bit for an oscillation period and thereupon outputting a count signal; detection logic coupled to said digital delay line and configured for outputting a busy signal indicative of whether or not a bit is being delayed by said digital delay line; feedback logic coupled to an output of said digital delay line, an input of said digital delay line, and an output of said detection logic and configured for applying a bit to be delayed by said digital delay line responsive to the busy signal, the count signal, and the start signal; a pre-scaler for outputting a scaled count signal based on the count signal and a scaling signal, wherein said prescaler is set to a prescribed logic in response to the start signal; a mantissa counter for counting occurrences of the scaled count signal and outputting an overflow count signal, wherein said mantissa counter is reset to a complementary logic state in response to the start signal; an exponent counter for counting occurrences of the overflow count signal, wherein said mantissa counter is reset to the complementary logic state in response to the start signal; and a shift register for doubling the scaling signal in response to the overflow count signal, wherein said prescaler is set to the prescribed logic state in response to the start signal; wherein the oscillation period substantially matches the delay period of a path through said pre-scaler to said mantissa counter to said shift register and back to said pre-scaler.
-
Specification