Digital matched filter

• US 5,903,595 A
• Filed: 02/27/1997
• Issued: 05/11/1999
• Est. Priority Date: 12/10/1996
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Suzuki, Kuniyuki
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Maddox, Michael W.
• Application Number:
  US08/804,978
• Time in Patent Office: 803 Days
• Field of Search: 375/207, 375/208, 375/343, 364/724.11
• US Class Current: 375/152
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

The digital matched filter according to the present invention comprises a storage circuit for accumulating received signals by an A/D converter without shifting the signals, an address signal generating circuit for controlling an address for accumulating output from the A/D converter there, a reference data generating circuit for generating spread code for receiving, a ring-formed shift register for shifting output from the reference data generating circuit, a multiplying circuit for multiplying output from the storage circuit not executing shifting by output from the shift register, an adding circuit for adding output from the multiplying circuit, and a timing signal generating circuit for controlling timing for the operations described above.

Claims

1. A digital matched filter for executing correlation processing of an input received spread spectrum signal with a spread code, comprising:

an input signal generating means for generating an input data array, said input signal generating means including

means for sampling a received spread spectrum signal according to a timing signal, said spread spectrum signal having been generated by applying a spread code array of specified spread code length n (wherein n is an integer greater than

     1) to an information signal having a plurality of information bits, and quantizing each sample of said received spread spectrum signal using a quantization interval of m bits (wherein m is an integer greater than

     1), and

a storage circuit having n storage locations, each storage location storing an m-bit quantized sample of said received spread spectrum signal, wherein said storage circuit outputs n m-bit samples of said received spread spectrum signal according to said timing signal as said input data array;

a reference signal generating means for outputting a reference data array of length n corresponding to said spread code array, said reference signal generating means including a shift register for incrementally shifting said reference data array according to said timing signal;

a multiplying circuit for multiplying said input data array by said reference data array and outputting multiplied data results; and

an adding circuit for adding together said multiplied data results and outputting the result as a correlation value.

2. A digital matched filter according to claim 1;

wherein said reference signal generating means generates and outputs a reference data array consisting of spread code repeated by a sampling time within one spread code length.

3. A digital matched filter according to claim 1 comprising:

a latch circuit for storing a second reference data array which is an output from a shift register and outputting the second reference data array as a new reference data array;

a second multiplying circuit for multiplying data in an input data array by corresponding data in said second reference data array and outputting a plurality of generated second multiplied data;

a second adding circuit for summing the plurality of second multiplied data and outputting a second correlation value generated as described above; and

a determining means for comparing the second correlation value, or a value obtained by summing up the second correlation value to input data, transmitted data for which is transparent in the system, once for every one spread code length or at a cycle shorter than one spread code length required in the system to a present reference correlation value and outputting a result of determination;

said digital matched filter selecting either the multiplied data outputted from the multiplying circuit or preset null data indicating no-input state according to the result of determination and inputting the selected data in the adding circuit.

4. A digital matched filter according to claim 3;

wherein said second multiplying circuit executes multiplication of only a portion of input data in an input data array outputted from the storage circuit by the corresponding second reference data and outputs second multiplied data.

5. A digital matched filter according to claim 3;

wherein said second multiplying circuit executes multiplication of only a portion of quantized bits among a plurality of quantized bits in the input data outputted from the storage circuit by the corresponding second reference data and outputs second multiplied data.

6. A digital matched filter according to claim 1 comprising:

a latch circuit for storing a second reference data array which is an output from a shift register and outputting the second reference data array as a new reference data array;

a second multiplying circuit for multiplying data in an input data array by corresponding data in said second reference data array and outputting a plurality of generated second multiplied data;

a second adding circuit for summing the plurality of second multiplied data and outputting a second correlation value generated as described above; and

a determining means for comparing the second correlation value, or a value obtained by summing up the second correlation value to input data, transmitted data for which is transparent in the system, once for every one spread code length or at a cycle shorter than one spread code length required in the system to a present reference correlation value and outputting a result of determination;

said digital matched filter selecting either the input data outputted from the storage circuit or preset null data indicating no-input state according to the result of determination and inputting the selected data in the multiplying circuit.

7. A digital matched filter according to claim 6;

wherein said second multiplying circuit executes multiplication of only a portion of input data in an input data array outputted from the storage circuit by the corresponding second reference data and outputs second multiplied data.

8. A digital matched filter according to claim 6;

wherein said second multiplying circuit executes multiplication of only a portion of quantized bits among a plurality of quantized bits in the input data outputted from the storage circuit by the corresponding second reference data and outputs second multiplied data.

9. A digital matched filter according to claim 1;

wherein, as for multiplied data in a portion exceeding one information bit length which is an object for correlation processing, a preset null data indicating no-input state is inputted in place of said multiplied data in the adding circuit.

10. A digital matched filter according to claim 9;

wherein said reference signal generating means generates and outputs a reference data array consisting of spread code repeated by a sampling time within one spread code length.

11. A digital matched filter according to claim 1;

wherein, as for input data in a portion exceeding one information bit length which is an object for correlation processing, a preset null data indicating no-input state is inputted in place of said input data in the multiplying circuit.

12. A digital matched filter according to claim 11;

wherein said reference signal generating means generates and outputs a reference data array consisting of spread code repeated by a sampling time within one spread code length.

13. A digital matched filter according to claim 1;

wherein said reference signal generating means generates and outputs a reference data array for reference data in a portion exceeding one information bit length which is an object for correlation processing by using said preset null data indicating no-input state in place of the spread code.

14. A digital matched filter according to claim 13;

wherein said reference signal generating means generates and outputs a reference data array consisting of spread code repeated by a sampling time within one spread code length.