System to improve trapping of I/O instructions in a peripheral component interconnect bus computer system and method therefor

• US 5,903,773 A
• Filed: 08/28/1996
• Issued: 05/11/1999
• Est. Priority Date: 08/28/1996
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Richardson, Nicholas Julian, Davis, Barry, Hicok, Gary
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): PATEL, GAUTAM
• Application Number:
  US08/704,281
• Time in Patent Office: 986 Days
• Field of Search: 395/838, 395/839, 395/837, 395/835, 395/750.06
• US Class Current: 710/19
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A system for trapping I/O instructions. The system is comprised of at least one peripheral controller for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when the peripheral controller senses a power off condition in a peripheral device. A system controller is coupled to the at least one peripheral controller for receiving the target abort signal from the at least one peripheral controller and for sequentially: issuing a system management interrupt (SMI) signal; counting a predetermined time period to allow recognition of the SMI signal; and issuing a cycle completion signal after counting the predetermined time period. A CPU is coupled to the system controller for issuing a plurality of I/O instructions and for receiving the SMI signal and the cycle completion signal from the system controller.

Claims

1. A system for trapping I/O instructions, comprising, in combination:

at least one peripheral controller means for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when said at least one peripheral controller senses an off condition;

system controller means coupled to said at least one peripheral controller means for receiving said target abort signal from said at least one peripheral controller means, for sequentially issuing a system management interrupt (SMI) signal after counting a predetermined time period to allow recognition of said SMI signal and for issuing a cycle completion signal after counting said predetermined time period;

CPU means coupled to said system controller means for issuing said plurality of I/O instructions and for receiving said SMI signal and said cycle completion signal from said system controller means;

CPU bus means coupled to said CPU means and to said system controller means for relaying of said plurality of I/O instructions from said CPU means to said system controller means and for sending said SMI signal from said system controller means to said CPU means; and

peripheral bus means coupled to said system controller means and to said at least one peripheral controller means for relaying said plurality of I/O instructions from said system controller means to said at least one peripheral controller means and for sending said target abort signal from said at least one peripheral controller means to said system controller means;

said system controller means comprises;

CPU bus to peripheral bus bridge means coupled to said CPU bus means and to said peripheral bus means for relaying all of said plurality of I/O instructions from said CPU bus means to said peripheral bus means and for receiving said target abort signal issued by said at least one peripheral controller means and transmitted via said peripheral bus means; and

Target Abort SMI Logic means coupled to said CPU bus to peripheral bus bridge means for receiving said target abort signal and thereupon transmitting said SMI signal to said CPU bus means, wherein said Target Abort SMI Logic means comprises;

delay means coupled to said peripheral bus means for receiving said target abort signal and for delaying assertion of said cycle completion signal for said predetermined time period;

logic means coupled to said delay means for receiving said target abort signal and for asserting said cycle completion signal to said CPU means after said delay means waits said predetermined time period; and

flip-flop means coupled to said logic means and said CPU means for asserting said SMI signal to said CPU means and for receiving a SMI signal acknowledgment when said CPU means acknowledges said SMI signal.

2. The system of claim 1 wherein said peripheral bus means is a peripheral component interconnect (PCI) bus.

3. The system of claim 1 further comprising peripheral device means coupled to said at least one peripheral controller means for receiving and acting upon said plurality of I/O instructions received from said at least one peripheral controller means.

4. The system of claim 3 wherein said at least one peripheral controller means comprises:

power status means coupled to said peripheral device means for informing said at least one peripheral controller means when said peripheral device means is turned off and unable to respond to one of said plurality of I/O instructions which is said un-executable I/O instruction; and

target abort generation means coupled to said peripheral bus for generating said target abort signal when said power status means determines that said peripheral device means is turned off.

5. The system or claim 1 further comprising;

a secondary peripheral bus;

at least one secondary peripheral controller means coupled to said secondary peripheral bus for receiving a plurality of secondary I/O instructions from said CPU means and for initiating trapping of an un-executable secondary I/O instruction by issuing a secondary target abort signal when said at least one secondary peripheral controller senses an off condition; and

PCI--PCI Bridge means coupled to said peripheral bus means and to said secondary peripheral bus for transferring information from said at least one secondary peripheral controller means to said system controller means.

6. The system of claim 5 further comprising secondary peripheral device means coupled to said at least one secondary peripheral controller means for receiving and acting upon said plurality of secondary I/O instructions received from said at least one secondary peripheral controller means.

7. The system of claim 6 wherein said at least one secondary peripheral controller means comprises:

power status means coupled to said secondary peripheral device means for informing said at least one secondary peripheral controller means when said secondary peripheral device means is turned off and unable to respond to one of said plurality of secondary I/O instructions which is said un-executable secondary I/O instruction; and

secondary target abort generation means coupled to said secondary peripheral bus for generating said secondary target abort signal when said power status means determines that said secondary peripheral device means is turned off.

8. A method of providing a system for trapping I/O instructions comprising the steps of:

providing at least one peripheral controller means for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when said at least one peripheral controller senses an off condition;

providing system controller means coupled to said at least one peripheral controller means for receiving said target abort signal from said at least one peripheral controller means, for sequentially issuing a system management interrupt (SMI) signal after counting a predetermined time period to allow recognition of said SMI signal and for issuing a cycle completion signal after counting said predetermined time period;

providing CPU means coupled to said system controller means for issuing said plurality of I/O instructions and for receiving said SMI signal and said cycle completion signal from said system controller means;

providing CPU bus means coupled to said CPU means and to said system controller means for relaying of said plurality of I/O instructions from said CPU means to said system controller means and for sending said SMI signal from said system controller means to said CPU means; and

providing peripheral bus means coupled to said system controller means and to said at least one peripheral controller means for relaying said plurality of I/O instructions from said system controller means to said at least one peripheral controller means and for sending said target abort signal from said at least one peripheral controller means to said system controller means;

said step of providing system controller means further comprising the steps of;

providing CPU bus to peripheral bus bridge means coupled to said CPU bus means and to said peripheral bus means for relaying all of said plurality of I/O instructions from said CPU bus means to said peripheral bus means and for receiving said target abort signal issued by said at least one peripheral controller means and transmitted via said peripheral bus means; and

providing Target Abort SMI Logic means coupled to said CPU bus to peripheral bus bridge means for receiving said target abort signal and thereupon transmitting said SMI signal to said CPU bus means, wherein said step of providing Target Abort SMI Logic means further comprises the steps of;

providing delay means coupled to said peripheral bus means for receiving said target abort signal and for delaying assertion of said cycle completion signal for said predetermined time period;

providing logic means coupled to said delay means for receiving said target abort signal and for asserting said cycle completion signal to said CPU means after said delay means waits said predetermined time period; and

providing flip-flop means coupled to said logic means and said CPU means for asserting said SMI signal to said CPU means and for receiving a SMI signal acknowledgment when said CPU means acknowledges said SMI signal.

9. The method of claim 8 wherein said step of providing peripheral bus means further comprises the step of providing a peripheral component interconnect (PCI) bus.

10. The method of claim 8 further comprising the step of providing peripheral device means coupled to said at least one peripheral controller means for receiving and acting upon said plurality of I/O instructions received from said at least one peripheral controller means.

11. The method of claim 10 wherein said step of providing at least one peripheral controller means further comprises the steps of:

providing power status means coupled to said peripheral device means for informing said at least one peripheral controller means when said peripheral device means is turned off and unable to respond to one of said plurality of I/O instructions which is said un-executable I/O instruction; and

providing target abort generation means coupled to said peripheral bus for generating said target abort signal when said power status means determines that said peripheral device means is turned off.

12. The method of claim 8 further comprising the steps of

providing a secondary peripheral bus;

providing at least one secondary peripheral controller means coupled to said secondary peripheral bus for receiving a plurality of secondary I/O instructions from said CPU means and for initiating trapping of an un-executable secondary I/O instruction by issuing a secondary target abort signal when said at least one secondary peripheral controller senses an off condition; and

providing PCI--PCI Bridge means coupled to said peripheral bus means and to said secondary peripheral bus for transferring information from said at least one secondary peripheral controller means to said system controller means.

13. The method of claim 12 further comprising the step of providing secondary peripheral device means coupled to said at least one secondary peripheral controller means for receiving and acting upon said plurality of secondary I/O instructions received from said at least one secondary peripheral controller means.

14. The method of claim 13 wherein said step of providing at least one secondary peripheral controller means further comprises the steps of:

providing power status means coupled to said secondary peripheral device means for informing said at least one secondary peripheral controller means when said secondary peripheral device means is turned off and unable to respond to one of said plurality of secondary I/O instructions which is said un-executable secondary I/O instruction; and

providing secondary target abort generation means coupled to said secondary peripheral bus for generating said secondary target abort signal when said power status means determines that said secondary peripheral device means is turned off.