Digital FM receiver back end

• US 5,903,825 A
• Filed: 06/27/1996
• Issued: 05/11/1999
• Est. Priority Date: 06/27/1996
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Goode, Steven Howard, Carney, Michael John, Baker, James Clark
• Primary Examiner(s): TO, DORIS HA
• Application Number:
  US08/671,385
• Time in Patent Office: 1,048 Days
• Field of Search: 455/205, 455/209, 455/210, 455/214, 455/337, 455/296, 455/303, 455/304, 455/305, 455/307, 455/314, 455/323, 375/346, 375/371, 375/375, 329/315, 329/341, 329/342, 329/343
• US Class Current: 455/205
• CPC Class Codes: H03D 3/006 by sampling the oscillations and further processing the samples, e.g. by computing techniques H03D3/007 takes precedence

Abstract

The digital FM receiver back end receives an analog intermediate frequency signal from a radio frequency front end (310) having a heterodyne circuit (312) and an intermediate frequency filter (314). In the receiver back end (307), a digital demodulator (330) having a hard limiter (333), a direct phase digitizer (336), and a phase differential circuit (339) produces a digital phase differential signal from the analog intermediate frequency signal. Next, a digital processor (360) filters and reduces noise in the digital phase differential signal using a bandpass filter (362), a de-emphasis filter (364), and an expandor (366). Finally, a pulse-width-modulation audio amplifier (380) prepares the signal for reproduction on an audio speaker (390). The digital FM receiver back end avoids inherent DC offset problems common to analog FM receivers, and it also offers a reduced complexity, size, and power consumption alternative to conventional digital FM receivers.

Claims

1. A digital FM receiver back end comprising:

a digital demodulator for demodulating an analog intermediate frequency signal to a digital baseband signal;

a digital processor connected to the digital demodulator, for filtering the digital baseband signal using bit-serial digital processing, wherein the digital processor comprises;

a bit-serial digital bandpass filter, for reducing the bandwidth of the digital baseband signal;

a bit-serial digital de-emphasis filter connected to the bit-serial bandpass filter, for compensating for high frequency noise amplification in the digital baseband signal; and

a bit-serial digital expandor connected to the bit-serial de-emphasis filter, for expanding the digital baseband signal; and

a converter block connected to the digital processor, for converting the digital baseband signal to an analog baseband signal.

2. A digital FM receiver back end according to claim 1 wherein the converter block comprises:

a pulse-width-modulation audio amplifier; and

an audio speaker connected to the pulse-width-modulation amplifier.

3. A digital FM receiver back end according to claim 1 wherein the digital demodulator comprises:

a hard limiter, for limiting the analog intermediate frequency signal to a limited intermediate frequency signal having two voltage levels;

a direct phase digitizer connected to the hard limiter, for converting the limited intermediate frequency signal to a digital phase word; and

a phase differential circuit connected to the direct phase digitizer, for converting the digital phase word to a digital phase differential word.

4. A digital FM receiver back end according to claim 3 wherein the digital phase differential word is one bit longer than the digital phase word.

5. A digital FM receiver back end according to claim 1 wherein the converter block comprises:

a sigma-delta converter.

6. An FM receiver comprising:

an FM receiver front end, for converting an analog radio frequency signal to an analog intermediate frequency signal; and

an FM receiver back end comprising;

a digital demodulator, for demodulating the analog intermediate frequency signal to a digital baseband signal;

a digital processor connected to the digital demodulator, for filtering the digital baseband signal using bit-serial digital processing, wherein the digital processor comprises;

a bit-serial digital bandpass filter, for reducing the bandwidth of the digital baseband signal;

a bit-serial digital de-emphasis filter connected to the bit-serial bandpass filter, for compensating for high frequency noise amplification in the digital baseband signal; and

a bit-serial digital expandor connected to the bit-serial de-emphasis filter, for expanding the digital baseband signal; and

a converter block connected to the digital processor, for converting the filtered digital baseband signal to an analog baseband signal.

7. An FM receiver according to claim 6 wherein the converter block comprises:

a pulse-width-modulation amplifier; and

an audio speaker connected to the pulse-width-modulation amplifier.

8. An FM receiver according to claim 6 wherein the FM receiver front end comprises:

a heterodyne circuit, for stepping down the analog radio frequency signal to an analog intermediate frequency signal; and

an intermediate frequency filter connected to the heterodyne circuit, for filtering the analog intermediate frequency signal.

9. A radiotelephone comprising:

an FM receiver comprising;

A) a radio frequency front end having a heterodyne circuit for producing an analog intermediate frequency signal from an analog radio frequency signal;

B) a digital demodulator connected to the radio frequency front end comprising;

1) a hard limiter, for limiting the analog intermediate frequency signal to a limited intermediate frequency signal having two voltage levels;

2) a direct phase digitizer connected to the hard limiter, for producing a digital phase word from the limited intermediate frequency signal; and

3) a phase differential circuit connected to the direct phase digitizer, for producing a digital phase differential word from the digital phase word;

C) a digital processor connected to the digital demodulator comprising;

1) a bit-serial digital bandpass filter, for reducing the bandwidth of the digital phase differential word;

2) a bit-serial digital de-emphasis filter connected to the bit-serial digital bandpass filter, for compensating for high frequency noise amplification; and

3) a bit-serial digital expandor connected to the bit-serial digital de-emphasis filter, for expanding the digital phase differential word to produce a digital signal; and

D) a pulse-width-modulation audio amplifier connected to the digital processor for converting the digital signal to a pulse-width-modulated signal.

10. A radiotelephone according to claim 9 further comprising:

an audio speaker connected to the pulse-width-modulation audio amplifier for converting the pulse-width-modulated signal into an audio signal.

11. A radiotelephone according to claim 9 wherein the digital phase differential word is one bit longer than the digital phase word.

12. A method for receiving FM signals comprising the steps of:

A) stepping down an analog radio frequency signal to produce an analog intermediate frequency signal;

B) digitally demodulating the analog intermediate frequency signal to produce a digital baseband signal comprising the steps of;

1) limiting the analog intermediate frequency signal to a limited intermediate frequency signal having two voltage levels;

2) directly digitizing the limited intermediate frequency signal to produce a digital phase word; and

3) taking a differential of the digital phase word to produce a digital phase differential word;

C) digitally processing the digital phase differential word comprising the steps of;

1) bit-serially bandpass filtering the digital phase differential word;

2) bit-serially de-emphasis filtering the digital phase differential word; and

3) bit-serially expanding the digital phase differential word to produce a digital signal; and

D) converting the digital signal to an audio signal.

13. An FM receiver back end comprising:

a demodulator, for demodulating an analog intermediate frequency signal to a digital baseband signal;

a digital processor connected to the digital demodulator, for filtering the digital baseband signal using bit-serial digital processing, wherein the digital processor comprises;

a bit-serial digital bandpass filter, for reducing the bandwidth of the digital baseband signal;

a bit-serial digital de-emphasis filter connected to the bit-serial bandpass filter, for compensating for high frequency noise amplification in the digital baseband signal; and

a bit-serial digital expandor connected to the bit-serial de-emphasis filter, for expanding the digital baseband signal; and

a converter block connected to the digital processor, for converting the digital baseband signal to an analog baseband signal.