Package for power semiconductor chips

• US 5,904,499 A
• Filed: 08/05/1997
• Issued: 05/18/1999
• Est. Priority Date: 12/22/1994
• Status: Expired due to Term

• Current Assignee: Network Protection Sciences, LLC (Innovation Management Sciences, LLC)
• Original Assignee: Benedict G. Pace
• Inventors: Pace, Benedict G
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/906,045
• Time in Patent Office: 651 Days
• Field of Search: 438/107, 438/108, 438/121, 438/125
• US Class Current: 438/108
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/053 the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

An electronic packaging module for bonding of power semiconductor devices is produced. The semiconductor device is mounted on a base, and enclosed by a frame and lid. The lid is an insulating substrate having a conductive pattern with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the metallization pads of semiconductor devices. The metal protuberances are bonded to the semiconductor device joining it to the lid, and through the conductive pattern of the lid connecting the device to the input/output contacts of the package.

Claims

1. In a method of packaging at least one semiconductor chip wherein a first surface of the chip is bonded to a base, the base being attached to a frame, and the frame attached to a lid to enclose the chip, the chip having at least one contact pad on its second surface, the improvement in the packaging method comprising:

providing as the lid a planar, rigid, insulating, substrate having at least one conductive pattern layer on a first surface facing the chip;

forming at least one soft, ductile, metal protuberance on at least one conductor of the conductive pattern layer on the first surface of the lid, and

connecting the conductive pattern of the lid to the chip by metallurgically bonding the protuberances to contact pads of the chip number of protuberances bonded to a contact pad being sufficient to minimize the contact resistance and the power lost as heat (I² R) between the chip and the lid, and minimize the current density on the surface of the chip.

2. The method of claim 1 wherein the insulating substrate is an inorganic substrate.

3. The method of claim 2 wherein the frame and the base are inorganic materials and the chip is hermetically enclosed.

4. The method of claim 1 wherein:

the conductive pattern layer on the first surface of the lid is at least partially covered by a permanent insulating layer;

openings are formed in the insulating layer, and

the protuberances on the conductive pattern layer are formed in the openings and protrude above the insulating layer.

5. In the method of claim 1 wherein:

the conductive pattern layer on the first surface of the lid is at least partially covered by a temporary insulating layer;

at least one opening is formed in the insulating layer;

forming the protuberances on the conductive pattern layer in the openings, and

removing the temporary insulating layer is, the protuberances remaining on the conductive pattern layer.

6. The method of claim 1 wherein the protuberances are metallurgically bonded to the chip by thermocompression, thermosonic or ultrasonic bonding.

7. The method of claim 6 wherein the size of the protuberances is sufficient to form reliable metallurgical bonds to the contact pad, and not so high that the protuberances could collapse and short circuit in the bonding process, or so large that the bonding pressure required for reliable metallurgical bonds could damage the chip.

8. The method of claim 1 wherein the protuberances comprise a soft, ductile metal selected from the group consisting of aluminum, copper, gold, indium, lead, silver, and alloys and combinations of these metals.

9. The method of claim 6 wherein the protuberances are formed by electrodepositing soft, ductile gold.

10. In a method according to claim 1, wherein the first surface of the chip is a power contact which is bonded to an electrically conductive base, and the frame is a conductive metal metallurgically bonded to the base;

the improvement comprising;

forming a conductive pattern on the first surface of the lid, the conductive pattern having a metallic conductor surrounding and insulated from first surface of the chip, and

forming a conductive bond between the frame and the said conductor which electrically connects the power contact on the first surface of the chip to the conductive pattern of the lid.

11. The method of claim 1, wherein the conductive pattern of the lid comprises conductive vias from a conductive pattern layer on the first surface of the lid through the lid providing electrical contacts from the first surface of the lid to the second surface of the lid.

12. The method of claim 11, wherein the conductive pattern of the lid includes a conductive pattern layer on the second surface of the lid.

13. In the method of claim 1, the improvement for ease of assembly comprising:

providing a base small enough to slide inside the frame;

bonding the chip to the base;

joining the frame and the lid;

placing the base with the chip thereon inside the frame, and metallurgically bonding the chip to the protuberances of the lid, the base freely sliding down inside the frame to compensate for the height changes during the bonding process and for variations due to the height of the protuberances and thickness tolerances of the lid, chip and base.

14. The method of claim 13 wherein the chip is metallurgically bonded to the protuberances while bonding the base to the frame.

15. In the method of claim 1, the improvement for ease of assembly comprising:

providing a lid small enough to slide inside the frame;

bonding the chip and frame to the base;

placing the lid inside the frame, and metallurgically bonding the protuberances of the lid to the chip, the lid freely sliding down inside the frame to compensate for the height changes during the bonding process and for variations due to the height of the protuberances and thickness tolerances of the lid, chip and base.

16. The method of claim 15 wherein the chip is metallurgically bonded to the protuberances while bonding the lid to the frame.

17. In the method of claim 1, the improvement for ease of assembly comprising:

providing a frame large enough to slide over the base and the lid;

bonding the chip to the base;

and metallurgically bonding the protuberances of the lid to the chip, the lid and base freely moving to compensate for the height changes during the bonding process and for variations due to the height of the protuberances and thickness tolerances of the lid, chip and base, and

sealing the base and lid inside the frame.

18. The method of claim 17 wherein the chip is metallurgically bonded to the protuberances while sealing the base and the lid inside the frame.

19. In a method of packaging a semiconductor chip wherein the chip is bonded to an inorganic base and enclosed by an inorganic frame and lid, a first surface of the chip being bonded to the base, and the chip having at least one contact pad on a second surface, the improvement comprising:

providing as the lid a planar, insulating, inorganic substrate, capable of being bonded to the frame, the lid having at least one conductive pattern layer on a first surface facing the chip;

forming at least one soft, ductile, metal protuberance on at least one conductor of the conductive pattern layer on the first surface the lid;

connecting the conductive pattern layer on the first surface of the lid to the chip by metallurgically bonding at least one protuberance to a contact pad of the chip, the number of protuberances bonded to a contact pad being sufficient to minimize the contact resistance and the power lost as heat (I² R) between the chip and the lid, and

bonding the lid and base to the frame to enclose the chip in an inorganic package.

20. In the method of claim 19, the improvement comprising forming a second conductive pattern layer on a second surface of the lid, the second conductive pattern layer being connected to the first conductive pattern layer, and the second conductive pattern layer being capable of connecting the package to a higher level of electronic packaging.

21. In the method of claim 19, the improvement wherein the conductive pattern of the lid also comprises passive electronic components.

22. The method of claim 21 wherein the passive components comprise a deposited resistor on the substrate to provide electrostatic discharge (ESD) protection.

23. In a method of packaging a semiconductor chip wherein a contact area of the chip is electrically connected to a conductive pattern on a rigid, planar, insulating substrate, the improvement comprising:

forming a plurality of soft, ductile metal protuberances on the conductive pattern of the insulating substrate;

placing the protuberances of the insulating substrate against the chip and metallurgically bonding the protuberances to the contact areas of the chip with multiple protuberances bonding to a contact area, the number of protuberances bonding to a contact area being sufficient to minimize contact resistance, power lost as heat (I² R) and to minimize the current density on the surface of the chip.

24. The method of claim 23 wherein the semiconductor chip has a plurality of semiconductor devices.

25. A method for packaging a plurality of semiconductor devices in a unitary package comprising:

providing a plurality of semiconductor chips, each chip having at least one semiconductor device;

bonding a first surface of each chip to a base, each chip having at least one contact pad on a second surface;

surrounding the chips by at least one frame;

providing a rigid, planar, insulating substrate as a common lid for the package;

forming a conductive pattern on the insulating substrate, the conductive pattern having at least one conductive pattern layer;

forming a plurality of soft, ductile metal protuberances on the conductive pattern layer;

metallurgically bonding the protuberances to contact pads on the second surfaces of the plurality of chips, the number of protuberances bonding to a contact pads being sufficient to minimize contact resistance and power lost as heat (I² R) between the chip and the lid, and minimize the current density on the surface of the chip, and

sealing the frame surrounding chips to the base and the common lid to enclose the semiconductor devices in a unitary package.

26. A method of packaging a plurality of semiconductor devices according to claim 25, wherein forming the conductive pattern on the lid comprises forming the conductive pattern layer and soft, ductile, metal protuberances on a first surface of the lid, and also forming at least one conductive pattern layer on a second surface of the lid adapted for input/output connections for the package;

the conductive pattern of the lid including through connections between the first and second surfaces.

27. A method of packaging a plurality of semiconductor devices according to claim 25, wherein the conductive pattern and the protuberances are formed on both the top and bottom surfaces of the lid, and semiconductor chips are metallurgically bonded to the protuberances on both the top and bottom surfaces of the lid.

28. A method of packaging a plurality of semiconductor devices according to claim 25, wherein each chip is individually enclosed by a frame.

29. A method of packaging a plurality of semiconductor devices according to claim 25, wherein the conductive pattern on the insulating substrate is formed so that it interconnects at least some of the semiconductor devices.

30. A method of packaging a plurality of semiconductor devices according to claim 25, wherein the frames are provided as one unit comprising an openwork, lattice structure.