Semiconductor device and a method of manufacturing the same

• US 5,904,508 A
• Filed: 01/21/1997
• Issued: 05/18/1999
• Est. Priority Date: 09/27/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd., TDK Corporation
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd., TDK Corporation
• Inventors: Arai, Michio, Codama, Mitsufumi
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): SULSKY, MARTIN S
• Application Number:
  US08/786,188
• Time in Patent Office: 847 Days
• Field of Search: 437/21, 437/40, 437/41, 437/44, 148/DIG. 141, 438/151, 438/163, 438/299, 438/303, 438/305, 438/585, 438/595, 438/947
• US Class Current: 438/151
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

Fabrication of TFTs utilizing self-aligned techniques. Although gate electrodes are made of aluminum, source/drain regions can be activated by a heat treatment. Spacers are formed, using dummy gate electrodes. Gate electrodes are defined, using the spacers. Impurity ions are implanted before the gate electrodes are formed. Thus, the source/drain regions, channel formation regions, and offset regions are formed in a self-alignment manner, using the dummy gate electrodes and the spacers as masks. Since the heat treatment is made before the formation of the gate electrodes, the gate electrodes can be formed from aluminum having a low melting point.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a semiconductor layer over a substrate;

forming a convex region comprising polysilicon or a silicide over said semiconductor layer;

implanting an impurity of a first concentration in said semiconductor layer by using said convex region as a mask;

forming spacers comprising an insulator on side surfaces of said convex region;

implanting an impurity of a second concentration in said semiconductor layer by using said convex region and said spacers as a mask;

annealing said semiconductor layer thereby activating said impurities of said first and second concentrations, after completion of said implanting of said impurities of first and second concentrations;

removing said convex region; and

forming a gate electrode comprising a metal after said annealing in a region defined by said spacers.

11. A method according to claim 1 wherein said semiconductor layer comprises polysilicon.

2. A method of manufacturing a semiconductor device comprising the steps of:

forming an active layer or active region having a gate-insulating film thereon;

forming a convex region comprising polysilicon or a silicide over said gate-insulating film;

forming spacers comprising an insulator on side surfaces of said convex region;

implanting impurity ions into said active layer or active region, using said convex region and said spacers as a mask;

performing a heat treatment after completion of said implanting of impurity ions;

removing said convex region; and

forming a gate electrode comprising aluminum in a region defined by said spacers after said heat treatment.

4. The method according to claim 2 wherein said active layer comprises polysilicon.

5. The method of claim 2, wherein said heat treatment is performed at a temperature which is higher than 600°

C. and lower than melting point of silicon, and wherein said gate electrode comprises aluminum.

6. The method of claim 2, wherein said gate electrode comprises a material which can not withstand a temperature used during said heat treatment.

3. A method of manufacturing a semiconductor device comprising the steps of:

forming an active layer or active regions having a gate-insulating film thereon;

forming a convex region comprising polysilicon or a silicide over said gate-insulating film;

forming spacers comprising an insulator on side surfaces of said convex region;

implanting impurity ions into said active layer or active region, using said convex region and said spacers as a mask;

performing a heat treatment to anneal said active layer or active regions after completion of implanting said impurity ions;

removing said convex region; and

forming a gate electrode comprising aluminum in a region defined by said spacers after said heat treatment,

wherein said heat treatment prior to formation of said gate electrode is conducted at such a high temperature that said gate electrode would be damaged if said gate electrode was exposed to said high temperature.

10. The method of claim 3, wherein said heat treatment is performed at a temperature which is higher than 600°

C. and lower than melting point of silicon.

12. A method according to claim 3 wherein said active layer comprises polysilicon.

7. A method of manufacturing a semiconductor device comprising the steps of:

forming a non-single crystalline semiconductor film over a substrate;

forming a gate insulating film over said semiconductor film;

forming a dummy electrode comprising polysilicon or a silicide over said gate insulating film;

forming side wall spacers comprising an insulating material on side surfaces of said dummy gate electrode;

introducing ions of an impurity into portions of said semiconductor film with said dummy gate electrode and said side wall spacers used as a mask;

annealing said semiconductor film after completion of said introduction of said impurity thereby activating said impurity;

etching said dummy electrode after said annealing whereby a groove is formed between said side wall spacers over said gate insulating film;

forming a conductive film comprising aluminum;

etching said conductive film comprising aluminum thereby forming a gate electrode within said groove;

wherein said heat treatment prior to formation of said gate electrode comprising aluminum is conducted at such a high temperature that said gate electrode would be damaged if said gate electrode was exposed to said high temperature.

13. A method according to claim 7 wherein said non-single crystalline semiconductor film comprises polysilicon.

8. A method of manufacturing a semiconductor device comprising the following sequential steps of:

forming a non-single crystalline semiconductor film over a substrate;

forming a gate insulating film over said semiconductor film;

forming a dummy electron over said gate insulating film;

introducing ions of a first impurity into said semiconductor film with said dummy electrode used as a first mask at a first concentration;

forming side wall spacers comprising an insulating material on side surfaces of said dummy electrode;

introducing ions of a second impurity into portions of said semiconductor film with said dummy electrode and said side wall spacers used as a second mask at a second concentration larger than said first concentration, thereby, forming lightly doped regions below said side wall spacers;

annealing said semiconductor film after completion of said introduction of said first and second impurities thereby activating said impurities; and

then

replacing said dummy electrode with a gate electrode comprising aluminum,

wherein said annealing step prior to formation of said gate electrode comprising aluminum is carried out at such a condition that said gate electrode would be damaged if said gate electrode was exposed to said high temperature.

9. A method according to claim 8 wherein said non-single crystalline semiconductor film comprises polysilicon.