Transistor structure and method for fabricating the same

• US 5,904,516 A
• Filed: 04/09/1997
• Issued: 05/18/1999
• Est. Priority Date: 11/26/1993
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Park, Sang Hoon
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US08/838,607
• Time in Patent Office: 769 Days
• Field of Search: 438/231, 438/234, 438/303, 438/202, 438/197
• US Class Current: 438/197
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor including an insulating file, a gate, and a source/drain all formed on a semiconductor substrate, wherein the gate overlaps at an edge thereof with the source/drain disposed below the gate, whereby the transistor has a structure capable of avoiding a direct contact between the metal wiring and the source/drain. The gate is formed after a formation of the source/drain.

Claims

1. A method for fabricating a transistor including an insulating film, a gate, and a source/drain all formed on a semiconductor substrate, the gate overlapping at an edge thereof with the source/drain disposed below the gate, the method comprising:

forming a field oxide film on the semiconductor substrate, sequentially forming an insulating film, a conduction film and another insulating film to predetermined thicknesses, and selectively etching the films such that the semiconductor substrate is exposed at a portion thereof disposed at a source/drain region;

implanting impurity ions in the exposed portion of the semiconductor substrate, thereby forming the source/drain;

forming a conduction film and an insulating film over the entire exposed surface obtained after the formation of the source/drain, and selectively etching the films, thereby forming a spacer disposed over the source/drain; and

forming another insulating film and a polysilicon film over the entire exposed surface including said spacers and selectively etching the films, thereby forming a gate insulating film and the gate.

2. A method in accordance with claim 1, wherein the polysilicon film and the insulating film both constituting the gate are a doped polysilicon film and a silicide film, respectively.

3. A method in accordance with claim 1, wherein the conduction film constituting the spacer is a doped polysilicon film.

4. A method in accordance with claim 1, wherein the insulating film constituting the spacer is formed using a low temperature deposition process.

5. A method in accordance with claim 1, wherein the method comprises the steps of:

forming a planarizing insulating film over the entire exposed surface of the resulting structure obtained after the formation of the gate;

selectively etching the planarizing insulating film and the insulating film disposed over the conduction film being in contact with the spacer disposed over the source/drain, thereby exposing a predetermined portion of the conduction film being in direct contact with the source/drain; and

forming a metal film on the exposed portion of the conduction film, thereby forming a metal wiring.

6. A method in accordance with claim 5, wherein the step of forming the planarizing insulating film comprises the steps of:

forming an oxide film over the entire exposed surface of the resulting structure obtained after the formation of the gate; and

forming a boro-phosphor-silicate-glass film for a planarization over the oxide film.