Trench scribe line for decreased chip spacing

• US 5,904,548 A
• Filed: 11/21/1996
• Issued: 05/18/1999
• Est. Priority Date: 11/21/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Orcutt, John W.
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/752,822
• Time in Patent Office: 908 Days
• Field of Search: 437/226, 437/227, 437/924, 148/DIG. 28, 438/460, 438/461, 438/462, 438/463
• US Class Current: 438/462
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

A method of scribing and separating chips on a semiconductor wafer (21) wherein the wafer (21) is patterned and a pattern of intersecting grooves is etched on a selected surface of the semiconductor wafer (21) in a pattern, preferably in a grid pattern, to define chip areas on that surface. Trenches (27) are then formed in the shape of the pattern and the selected surface is adhered to a tape (29). Light is then passed through the tape (29) and semiconductor wafer (21) from the pattern and a pattern of intersecting saw cuts or grooves (28) aligned with the light passing through the wafer (21) is formed. The saw cuts (28) extend from a surface of the wafer (21) opposing the selected surface and are aligned with the pattern of intersecting trenches (27).

Claims

1. A method of separating chips on a semiconductor wafer comprising the steps of:

(a) providing a semiconductor wafer;

(b) etching a pattern of intersecting trenches on a selected surface of said wafer to define chip areas on said surface;

(c) forming a groove extending from a surface of said wafer opposing said selected surface aligned with said pattern of intersecting trenches; and

(d) breaking the region of semiconductor material in said wafer between said groove and said pattern of intersecting trenches to form individual chips.

2. The method of claim 1 wherein said step of etching a pattern includes the steps of masking said selected surface to define a grid pattern and then etching said grid pattern to form said trenches.

3. The method of claim 1 wherein said step of forming a groove comprises the steps of passing detectable energy through said semiconductor wafer from said trenches and then forming said groove aligned with said energy passing through said trenches.

4. The method of claim 2 wherein said step of forming a groove comprises the steps of passing detectable energy through said semiconductor wafer from said trenches and then forming said groove aligned with said energy passing through said trenches.

5. The method of claim 3 wherein said energy is a light having a frequency transmissive through said semiconductor wafer, said step of forming a groove further comprises the step of adhering said wafer to a tape transmissive to light having said frequency prior to passing light through said wafer.

6. The method of claim 4 wherein said energy is a light having a frequency transmissive through said semiconductor wafer, said step of forming a groove further comprises the step of adhering said wafer to a tape transmissive to light having said frequency prior to passing light through said wafer.