Low resistance contact between integrated circuit metal levels and method for same

• US 5,904,565 A
• Filed: 07/17/1997
• Issued: 05/18/1999
• Est. Priority Date: 07/17/1997
• Status: Expired due to Fees

• Current Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), Sharp Microelectronics Technology, Inc.
• Inventors: Nguyen, Tue, Hsu, Sheng Teng
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US08/896,114
• Time in Patent Office: 670 Days
• Field of Search: 438/608, 438/656, 438/660, 438/686, 438/687, 438/643, 438/644, 438/655, 438/672, 438/622, 438/637, 438/638, 438/666
• US Class Current: 438/687
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.

Claims

1. In an integrated circuit (IC) via having sidewall surfaces and passing through a dielectric interlevel to expose selected areas of a metal level, a method for forming sidewall barriers lining a low resistance via interconnect without an intervening barrier layer between metal levels comprising the following steps:

a) conformally depositing a barrier layer material overlying the via to form a barrier layer overlying the dielectric interlevel sidewall surfaces and metal level selected areas; and

b) anisotropically etching to selectively remove the barrier layer deposited over the metal level selected areas, exposing the metal level selected areas, but not the dielectric interlevel sidewall surfaces, whereby a via, having barrier surface sidewalls, is prepared to directly connect the metal level with a subsequently deposited metal level for improved electrical conductivity.

2. In an integrated circuit (IC) including a first metal horizontal level, a first barrier layer overlying the first metal level, a first dielectric interlevel overlying the first barrier layer, and a second barrier layer overlying the first dielectric interlevel, a method for forming sidewall barriers lining a low resistance interconnect without an intervening barrier layer between metal levels comprising the following steps:

a) etching selected overlying areas of the first barrier layer, the first dielectric interlevel, and the second barrier layer to form a via, exposing vertical sidewall surfaces of the first dielectric interlevel and selected areas of the first metal level;

b) conformally depositing a third barrier layer over the vertical sidewall surfaces of the first dielectric interlevel and the first metal level selected areas exposed in step a); and

c) anisotropically etching, in the horizontal direction, to selectively remove the third barrier layer deposited over the first metal level selected areas, exposing the first metal level selected areas, but not the vertical sidewall surfaces of the first dielectric interlevel, whereby a via, having barrier surface sidewalls, is prepared to directly connect the first metal level with a subsequently deposited metal level for improved electrical conductivity.

3. A method as in claim 2 comprising the further step, following step c), of:

d) depositing a second metal level overlying the second barrier layer, filling the via formed in step a), to connect with the first metal level, whereby a minimum resistance connection, without an intervening barrier layer, is made between the metal levels.

4. A method as in claim 3 comprising the further step, following step d), of:

e) selectively etching the second metal level, forming an interconnect;

f) depositing a fourth barrier layer overlying the second metal level, and a second dielectric interlevel overlying the fourth barrier layer;

g) performing a chemical mechanical polish of the second dielectric interlevel, and depositing a fifth barrier layer overlying the second dielectric interlevel; and

h) repeating the steps of the method described in steps a) through d) to form a low resistance connection between the second metal level and a subsequently deposited third metal level, whereby a plurality of metal levels in the IC are interconnected.

5. A method as in claim 2 in which the first and second barrier layer materials are non-conductive, and the third barrier layer material is selected from the group consisting of conductive and nonconductive materials.

6. method as in claim 5 in which the non-conductive barrier layer material is selected from the group consisting of Si₃ N₄ and TiO.

7. A method as in claim 5 in which the conductive barrier layer material is selected from the group consisting of refractory metals and refractory metal compounds including TiN, WN, and TaN.

8. A method as in claim 2 in which the first metal level is copper.

9. A method as in claim 3 in which the first and second metal levels are copper.

10. In an integrated circuit (IC) damascene interconnection trench, having sidewall surfaces and passing through a second thickness of the dielectric interlevel, exposing selected areas of a first thickness of the dielectric interlevel overlying a metal level, a method for forming a dual damascene interconnect with sidewall barriers lining the trench and via, without forming an intervening barrier layer between the metal level and the dual damascene interconnect, the method comprising the following steps:

a) anisotropically depositing an insulating barrier layer material overlying the trench, forming an insulating barrier layer overlying the selected areas of the dielectric interlevel first thickness where a via is subsequently formed;

b) etching selected overlying areas of the insulating barrier layer and the underlying dielectric interlevel first thickness, exposing sidewall surfaces of the dielectric interlevel first thickness and selected areas of the metal level, whereby a via is formed from the trench to the metal level selected areas;

c) conformally depositing a conductive barrier layer material overlying the trench and via, forming a conductive barrier layer on the sidewall surfaces of the dielectric interlevel first and second thicknesses and the metal level selected areas, whereby all the dual damascene surfaces are covered with the conductive barrier layer; and

d) anisotropically etching, to selectively remove the conductive barrier layer overlying the metal level selected areas, exposing the metal level selected areas, but not the conductive barrier layer overlying the sidewall surfaces of the first dielectric interlevel first and second thicknesses, whereby a damascene process via and trench, having conductive barrier sidewall surfaces, are prepared to directly connect the metal level with a subsequently deposited copper metal level, without an intervening barrier layer, for improved conductivity.

11. A method as in claim 10 in which step b) exposes selected areas of a metal level material selected from the group consisting of aluminum, aluminum-copper alloys, and tungsten.

12. In an integrated circuit (IC) including a first metal horizontal level, a first barrier horizontal layer overlying the first metal level, and a first dielectric interlevel overlying the first barrier layer, the first dielectric interlevel having a first thickness and second thickness overlying the first thickness, a method for forming vertical sidewall barriers lining a low resistance dual damascene interconnect between metal levels without a horizontal barrier layer intervening between the first metal level and the dual damascene interconnect comprising the following steps:

a) etching selected areas of the first dielectric interlevel second thickness, forming a damascene interconnection trench, and exposing vertical sidewall surfaces of the first dielectric interlevel second thickness and selected horizontal surfaces of the first dielectric interlevel first thickness;

b) anisotropically depositing, in a horizontal direction, a second barrier layer over the first dielectric interlevel, to overlie the selected horizontal surfaces of the first dielectric interlevel first thickness exposed in step a), and minimally cover the vertical sidewall surfaces of the first dielectric interlevel second thickness;

c) etching selected overlying areas of the second barrier layer deposited in step b), selected horizontal surfaces of the first dielectric interlevel first thickness, and the first barrier layer, exposing vertical sidewall surfaces of the first dielectric interlevel first thickness and selected areas of the first metal level, whereby a via is formed from the trench to the first metal level selected areas;

d) conformally depositing a third barrier layer over the vertical sidewall surfaces of the first dielectric interlevel second thickness exposed in step a), the second barrier layer deposited in step b), and the first metal level selected areas and vertical sidewall surfaces of the first dielectric interlevel first thickness exposed in step c);

e) anisotropically etching, in the horizontal direction, to selectively remove the third barrier layer overlying the first metal level selected areas, exposing the first metal level selected areas, but not the third barrier layer overlying the vertical sidewall surfaces of the first dielectric interlevel first and second thicknesses, whereby a damascene process via and trench, having barrier surface sidewalls, are prepared to directly connect the first metal level with a metal subsequently deposited in the dual damascene structure for improved electrical conductivity.

13. A method as in claim 12 comprising the further step, following step e), of:

f) depositing a second metal level overlying the second barrier layer, filling the trench formed in step a) and the via formed in step b), to connect with the first metal level, whereby a minimum resistance connection, without an intervening barrier layer, is made between the metal levels.

14. A method as in claim 13 comprising the further step, following step f), of:

g) performing a chemical mechanical polish (CMP) of the second metal level;

h) depositing a fourth barrier layer overlying the second metal level, and a second dielectric interlevel overlying the fourth barrier layer;

j) repeating the steps of the method described in steps a) through f) to form a low resistance connection between the second metal level and a subsequently deposited metal level, whereby a plurality of metal levels in the IC are interconnected.

15. A method as in claim 12 in which the first and second barrier layer materials are non-conductive, and the third barrier layer material is selected from the group consisting of conductive and non-conductive materials.

16. A method as in claim 15 in which the non-conductive barrier layer material is selected from the group consisting of Si₃ N₄ and TiO.

17. A method as in claim 15 in which the conductive barrier layer material is selected from the group consisting of refractory metals, and refractory metal compounds including TiN, WN, and TaN.

18. A method as in claim 12 in which the first metal level is copper.

19. A method as in claim 13 in which the first and second metal levels are copper.