Bootstrap processor selection architecture in SMP systems

• US 5,904,733 A
• Filed: 07/31/1997
• Issued: 05/18/1999
• Est. Priority Date: 07/31/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jayakumar, Muthurajan
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Vo, Tim T.
• Application Number:
  US08/904,109
• Time in Patent Office: 656 Days
• Field of Search: 395/651, 395/652, 395/653
• US Class Current: 713/2
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity codes. If no processor having a lower valued identity code responds to the election message, the processor that originated the election message designates itself as the bootstrap processor and sends a message to all processors indicating itself as the bootstrap processor.

Claims

1. A method for selecting a bootstrap processor (BSP) in a multiprocessor (MP) system that includes a plurality of processors which communicate via a system bus, each processor including a register to store a processor identification (ID) having a value, the method comprising the steps of:

(a) asserting a reset signal;

(b) detecting the reset signal by each of the processors which are functioning in the MP system, each functional processor responding by;

(i) sending a first message, which includes the processor ID of the functional processor, across the system bus to all processors with processor IDs having values lower than the value associated with the functional processor; and

(ii) waiting a selected interval for a responsive message from one of the lower valued processors;

if the responsive message is not received within the selected interval, the functional processor being selected as the BSP;

otherwise,

the functional processor being selected as not the BSP.

2. The method according to claim 1 further comprising the step of:

(c) sending, by a functional processor having a lowest value processor ID, a selection message across the system bus, the selection message indicating that the functional processor having the lowest value processor ID is the BSP.

3. The method according to claim 1, wherein the reset signal is a warm reset signal.

4. The method according to claim 1, wherein the reset signal is a cold reset signal.

5. The method according to claim 4, further comprising the step, before step (i), of:

running a built-in, self-test routine by each of the processors.

6. The method according to claim 1, further comprising the step of:

storing the processor ID of the BSP in a non-volatile memory location of the MP system.

7. A storage medium on which is stored data for execution by one or more processors in a multiprocessor (MP) system, the processors communicating via a system bus with each processor including a register to store a processor identification (ID) having a value, execution of the data implementing a method comprising the steps of:

(a) asserting a reset signal;

(b) detecting the reset signal by each of the processors which are functional in the MP system, each functional processor responding by;

(i) sending a first message, which includes the processor ID of the functional processor, across the system bus to all processors with processor Ids having values lower than the value associated with the functional processor; and

(ii) waiting a selected interval for a responsive message from one of the lower valued processors;

if the responsive message is not received within the selected interval, the functional processor being selected as the BSP;

otherwise,

the functional processor being selected as not the BSP.

8. A multiprocessor system, which comprises:

a plurality of processors, each processor including a register to store a processor identification (ID) having a value;

a system bus coupled to the plurality of processors; and

a memory device coupled to the system bus; and

wherein each of the processors further includes means for selecting a bootstrap processor (BSP), the means operating responsive to a reset signal to send a first message, which includes the processor ID of the processor, across the system bus to all processors with processor IDs having values lower than the value associated with the processor;

the processor then waiting a selected interval for a responsive message from one of the lower valued processors;

if the responsive message is not received within the selected interval, the functional processor being selected as the BSP;

otherwise, the functional processor being selected as not the BSP.

9. The MP system of claim 8, further comprising a memory device that stores the processor ID of the BSP.

10. The MP system of claim 8, wherein each processor further includes a local interrupt controller for handling interrupt messages.