Low resistant trench fill for a semiconductor device
First Claim
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1. A memory cell structure comprising:
- a semiconductor substrate;
a trench formed in said semiconductor substrate;
a first trench fill formed in said trench, including a first conductive region of at least first and second conductive materials, and functioning as a storage node electrode of the capacitor, said first conductive material being a first impurity-doped conductive material and said second conductive material being a material other than polysilicon;
an insulating layer formed on the sidewall of said trench above said first trench fill;
a second trench fill formed on said first conductive region and including a second conductive region;
a third trench fill formed on said second conductive region and said insulating layer and including a third conductive region;
a transistor having a source/drain region adjacent to an intersection of said trench and the surface of said semiconductor substrate; and
a strap for electrically connecting said first and second conductive materials in said trench to said source/drain region.
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Abstract
A memory cell having a low storage node resistance and a method of manufacturing the same are provided. A trench type memory cell, in addition to storage node polysilicon, has other conductive material embedded in the storage node. Conductive material may be one of WSi, TiSi, W, Ti, and TiN. The additional conductive material provides a low storage node resistance which facilitates the realization of 256 Mbit memory cells and beyond.
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Citations
28 Claims
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1. A memory cell structure comprising:
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a semiconductor substrate; a trench formed in said semiconductor substrate; a first trench fill formed in said trench, including a first conductive region of at least first and second conductive materials, and functioning as a storage node electrode of the capacitor, said first conductive material being a first impurity-doped conductive material and said second conductive material being a material other than polysilicon; an insulating layer formed on the sidewall of said trench above said first trench fill; a second trench fill formed on said first conductive region and including a second conductive region; a third trench fill formed on said second conductive region and said insulating layer and including a third conductive region; a transistor having a source/drain region adjacent to an intersection of said trench and the surface of said semiconductor substrate; and a strap for electrically connecting said first and second conductive materials in said trench to said source/drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 26)
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14. A memory cell structure comprising:
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a semiconductor substrate; an insulating layer formed on top of said semiconductor substrate; first and second trenches formed in said semiconductor substrate and separated from each other by said insulating layer; a first trench fill formed in said first trench, including a first conductive region of at least first and second conductive materials, and functioning as a storage node electrode of the first capacitor, said first conductive material being a first impurity-doped conductive material and said second conductive material being a material other than polysilicon; a second trench fill formed in said second trench, including a second conductive region of at least said first and second conductive materials, and functioning as a storage node electrode of the second capacitor; a first transistor having a first source/drain region adjacent to an intersection of said first trench and said insulating layer; a first strap for electrically connecting said first and second conductive materials in said first trench to said source/drain region; a second transistor having a second source/drain region adjacent to an intersection of said second trench and said insulating layer; and a second strap for electrically connecting said first and second conductive materials in said second trench to said second source/drain region. - View Dependent Claims (15, 16, 27)
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17. A memory cell structure comprising:
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a semiconductor substrate; a trench formed in said semiconductor substrate; a first trench fill including a first conductive region of first and second conductive materials, said first conductive material being a first impurity-doped conductive material and said second conductive material being a material other than polysilicon; an insulating layer formed on a sidewall of the portion of said trench above said first trench fill; a second trench fill formed on said first conductive region and having a second conductive region, said second conductive region including at least said first conductive material and a third conductive material, said third conductive material being a material other than polysilicon; a third trench fill formed on said second conductive region and said insulating layer and having a third conductive region, said third conductive region including at least said first conductive material and a fourth conductive material, said fourth conductive material being a material other than polysilicon; a transistor having a source/drain region adjacent to an intersection of said trench and the surface of said semiconductor substrate; and a strap for electrically connecting said first and second conductive materials in said trench to said source/drain region. - View Dependent Claims (18, 19, 20, 28)
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21. A memory cell structure comprising:
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a semiconductor substrate; a trench formed in the semiconductor substrate; a first trench fill disposed in the trench and including a first conductive region of at least first and second conductive materials, the first conductive material being a first impurity-doped conductive material and the second conductive material being a material other than polysilicon, wherein the first trench fill functions as a storage node electrode of a capacitor; a second trench fill formed on the first conductive region and having a second conductive region; and a third trench fill formed on the second conductive region and having a third conductive region. - View Dependent Claims (22, 23, 24, 25)
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Specification