Semiconductor device with high voltage protection

• US 5,905,287 A
• Filed: 04/17/1997
• Issued: 05/18/1999
• Est. Priority Date: 04/25/1996
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Hirata, Morihisa
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/837,344
• Time in Patent Office: 761 Days
• Field of Search: 257/355-363
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

The object of the present invention is to provide a semiconductor device, which has a high protective capability against an excessive voltage applied from the outside. The device is provided, in its analog switch 30, with a P type dummy transistor 11 whose drain terminal is connected to a P type diffusion layer in the outside of a P type transfer gate 4 and whose gate and source terminals are connected to a power supply potential, and an N type dummy transistor 12 whose drain terminal is connected to an N type diffusion layer in the outside of an N type transfer gate 5 and whose gate and source terminals are connected to a ground potential, and when an excessive voltage is applied from the outside, an excessive current is made to flow through the P type and N type dummy transistors 11 and 12 to the power supply potential or the ground potential.

Claims

1. A semiconductor device comprising:

a plurality of pads for performing signal inputting and outputting, said pads comprising an input pad and an output pad;

an analog switch, which is provided with P type and N type MOS transistors for transmitting signals among said pads, said N type MOS transistor comprising first and second N type diffusion layers separated by a gate of said N type MOS transistor, said first N type diffusion layer connected to said input pad and said second N type diffusion layer connected to said output pad; and

a protective circuit, which is provided with P type and N type protective MOS transistors for protecting said analog switch,

wherein said analog switch is further provided with an N type dummy transistor, said N type dummy transistor being formed by using said first N type diffusion layer as a drain and connecting a gate and a source to a ground potential.

2. The semiconductor device according to claim 1, wherein said P type MOS transistor comprises first and second P type diffusion layers separated by a gate of said P type MOS transistor, said first P type diffusion layer connected to said input said and said second P type diffusion layer connected to said output pad, and wherein said analog switch is further provided with a P type dummy transistor, said P type dummy transistor being formed by using said first P type diffusion layer as a drain and connecting a gate and a source to a power supply potential.

3. The semiconductor device according to claim 1, wherein said N type protective MOS transistor is formed using said first N type diffusion layer as a drain.

5. The semiconductor device according to claim 2, wherein said P type protective MOS transistor is formed using said first P type diffusion layer as a drain.

4. A semiconductor device comprising:

a plurality of pads for performing signal inputting and outputting, said pads comprising an input pad and an output pad;

an analog switch, which is provided with P type and N type MOS transistors for transmitting signals among said pads, said P type MOS transistor comprising first and second P type diffusion layers separated by a gate of said P type MOS transistor, said first P type diffusion layer connected to said input pad and said second P type diffusion layer connected to said output pad; and

a protective circuit, which is provided with P type and N type protective MOS transistors for protecting said analog switch,

wherein said analog switch is further provided with a P type dummy transistor, said P type dummy transistor being formed by using said first P type diffusion layer as a drain and connecting a gate and a source to a power supply potential.

6. A semiconductor device comprising:

a plurality of pads for performing signal inputting and outputting, said pads comprising input pad and an output pad;

an output circuit, which is provided with first and second P type MOS transistors connected to each other in series between a power supply potential and said output pad, said first P type MOS transistor comprising first and second P type diffusion layers separated by a gate of said first P type MOS transistor, said first P type diffusion layer connected to said output sad; and

a protective circuit, which is provided with P type and N type protective MOS transistors for protecting said output circuit,

wherein said output circuit is further provided with a P type dummy transistor, said P type dummy transistor being formed by using said first P type diffusion layer as a drain and connecting a gate and a source to said power supply potential.

7. The semiconductor device according to claim 6, wherein said output circuit is a NOR type output circuit.

8. The semiconductor device according to claim 6, wherein said P type protective MOS transistor is formed using said first P type diffusion layer as a drain.

9. A semiconductor device comprising:

a plurality of pads for performing signal inputting and outputting, said pads comprising an input pad and an output pad;

an output circuit, which is provided with first and second N type MOS transistors connected to each other in series between a ground potential and said output pad, said first N type MOS transistor comprising first and second N type diffusion layers separated by a gate of said first N type MOS transistor, said first N type diffusion layer being connected to said output pad; and

a protective circuit, which is provided with P type and N type protective MOS transistors for protecting said output circuit,

wherein said output circuit is further provided with an N type dummy transistor, said N type dummy transistor being formed by using said first N type diffusion layer as a drain and connecting a gate and a source to said ground potential.

10. The semiconductor device according to claim 9, wherein said output circuit is a NAND type output circuit.

11. The semiconductor device according to claim 9, wherein said N type protective MOS transistor is formed using said first N type diffusion layer as a drain.