Single event upset hardened memory cell
First Claim
Patent Images
1. A bi-stable logic device comprising:
- first and second inverters each said first and second inverters including an input and an output;
a first resistor between the input of said first inverter and the output of said second inverter;
a second resistor coupled between the input of said second inverter and the output of said first inverter;
a capacitive coupling between the input of said first inverter and the output of said first inverter such that said first resistor isolates said capacitive coupling from the output of said second inverter and said second resistor isolates said capacitive coupling from the input of said second inverter.
0 Assignments
0 Petitions
Accused Products
Abstract
A bi-stable logic device 110 comprises first and second inverters 112 and 114. A first resistive connection 140 is made between the input 134 of the first inverter 112 and the output B-- of the second inverter 114 and a second resistive connection 142 is made between the input 138 of the second inverter 114 and the output B of the first inverter 112. The first and said second resistive connections are also capacitively coupling. The device 110 is hardened from single event upset. Other systems and methods are also disclosed.
-
Citations
32 Claims
-
1. A bi-stable logic device comprising:
-
first and second inverters each said first and second inverters including an input and an output; a first resistor between the input of said first inverter and the output of said second inverter; a second resistor coupled between the input of said second inverter and the output of said first inverter; a capacitive coupling between the input of said first inverter and the output of said first inverter such that said first resistor isolates said capacitive coupling from the output of said second inverter and said second resistor isolates said capacitive coupling from the input of said second inverter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 18, 19)
-
-
14. An integrated circuit device comprising:
-
an insulating layer formed on a semiconductor substrate; a semiconductor layer formed on said insulating layer; first and second inverters formed in said semiconductor layer each of said first and second inverters including an input and an output; a first resistor between the input of said first inverter and the output of said second inverter; a second resistor coupled between the input of said second inverter and the output of said first inverter; a capacitive coupling between the input of said first inverter and the output of said first inverter such that said first resistor isolates said capacitive coupling from the output of said second inverter and said second resistor isolates said capacitive coupling from the input of said second inverter. - View Dependent Claims (15, 16, 17)
-
-
20. An electronic latch with enhanced dynamic negative feedback comprising:
-
first and second elements wherein negative feedback is provided by capacitive coupling from an input of said first element to an output of said first element; and an isolation element connected between said input of said first element and an output of said second element. - View Dependent Claims (21, 22, 26, 27)
-
-
23. An integrated circuit memory device comprising:
-
first and second inverters formed in a semiconductor layer, each said first and second inverters including an input region and an output region; a first resistive region formed in said semiconductor layer, said first resistive region coupling said input of said first inverter to said output of said second inverter; an insulating layer formed over said first resistive region; a resistive layer formed over said insulating layer; and a second resistive region coupling said input of said second inverter to said output of said first inverter, said second resistive region formed in said resistive layer. - View Dependent Claims (24, 25)
-
-
28. An integrated circuit memory device comprising:
-
first and second inverters formed in a semiconductor layer, each said first and second inverters including an input region and an output region; a first resistive region coupling said input of said first inverter to said output of said second inverter; an insulating layer formed over said first resistive region; a resistive layer formed over said insulating layer; and a second resistive region coupling said input of said second inverter to said output of said first inverter, said second resistive region formed in said resistive layer. - View Dependent Claims (29, 30, 31, 32)
-
Specification