CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments

• US 5,905,386 A
• Filed: 02/27/1998
• Issued: 05/18/1999
• Est. Priority Date: 01/02/1996
• Status: Expired due to Term

• Current Assignee: Pmc-Sierra Limited (Microchip Technology Incorporated)
• Original Assignee: Pmc-Sierra Limited (Microchip Technology Incorporated)
• Inventors: Gerson, Brian Donald
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/031,715
• Time in Patent Office: 445 Days
• Field of Search: 326/73, 326/68, 326/69, 326/70, 326/71, 326/72, 326/74, 326/17, 326/62, 326/63, 326/83
• US Class Current: 326/73
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.

Claims

1. A pulse receiver, comprising:

(a) a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals,

(b) CMOS means for distorting said first pulse signals, to create second pulse signals from said converter having a duty cycle having a longer low logic level interval than high logic level interval,

(c) a CMOS latch for receiving and latching said second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements,

(d) a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals,

(e) means for providing an output signal referenced to VDD and ground from said converter.

2. A pulse receiver as defined in claim 1 including a CMOS differential comparator connected between outputs of the common gate amplifiers and the latch for receiving said pair of pulse output signals and for canceling common mode noise signals contained in said pulse output signals.

3. A pulse receiver as defined in claim 1 including means for fixing operating points of said common gate amplifiers to about 1.3 volts below ECL voltage level.

4. A pulse receiver as defined in claim 1 further including a multiplexer, means for applying one of the input signals and said output signal to respective inputs of the multiplexer, means for applying another of the input signals to a control input of the multiplexer, and means for receiving a CMOS output signal from the multiplexer in the event said another of the input signals is a TTL pulse signal and for receiving a CMOS output signal from the multiplexer.

5. A pulse receiver as defined in claim 4 including a CMOS differential comparator connected between outputs of the common gate amplifiers and the latch for receiving said pair of pulse output signals and for canceling common mode noise signals contained in said pulse output signals.

6. A pulse receiver as defined in claim 5 further including a multiplexer, means for applying one of the input signals and said output signal to respective inputs of the multiplexer, means for applying another of the input signals to a control input of the multiplexer, and means for receiving a pseudo ECL (PECL) output signal from the multiplexer in the event said another of the input signals is a PECL pulse signal.