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CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments

  • US 5,905,386 A
  • Filed: 02/27/1998
  • Issued: 05/18/1999
  • Est. Priority Date: 01/02/1996
  • Status: Expired due to Term
First Claim
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1. A pulse receiver, comprising:

  • (a) a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals,(b) CMOS means for distorting said first pulse signals, to create second pulse signals from said converter having a duty cycle having a longer low logic level interval than high logic level interval,(c) a CMOS latch for receiving and latching said second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements,(d) a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals,(e) means for providing an output signal referenced to VDD and ground from said converter.

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