Capacitor array having user-adjustable, manufacturer-trimmable capacitance and method

• US 5,905,398 A
• Filed: 04/08/1997
• Issued: 05/18/1999
• Est. Priority Date: 04/08/1997
• Status: Expired due to Term

• Current Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Kalthoff, Timothy V., Todsen, James L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ADOLPHE, EUNJA
• Application Number:
  US08/827,725
• Time in Patent Office: 770 Days
• Field of Search: 327/361, 327/356, 327/337, 327/339, 327/344, 327/345, 327/71, 327/74, 327/75, 327/525, 330/282, 341/172, 341/121, 365/96, 365/225.7
• US Class Current: 327/337
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Claims

1. An integrated circuit capacitor array having first and second ports and presenting a selectable desired capacitance between the first and second ports, comprising in combination:

(a) a plurality of capacitors each having a first terminal coupled to the first port, and also having a second terminal;

(b) a plurality of switches, each of the switches having a control electrode, a first main electrode, and a second main electrode, the first main electrode of each switch being coupled to the second port, the second main electrode of that switch being coupled to the second terminal of a corresponding one of the capacitors;

(c) a control circuit having a plurality of capacitance selection inputs representing the desired capacitance and a plurality of trim inputs representing a deviation from nominal of the capacitances of the capacitors, the control circuit producing a plurality of selection signals on the control electrodes of the plurality of switches, respectively, in response to the plurality of capacitance selection inputs in conjunction with the plurality of trim inputs to select one or more of the switches and the capacitors coupled thereto to couple the selected capacitors in parallel between the first and second ports and thereby provide between the first and second ports an accurate value of the desired capacitance despite any deviations from nominal of the capacitances of the capacitors.

2. An integrated circuit capacitor array having first and second ports and presenting a selectable desired capacitance between the first and second ports, comprising in combination:

(a) a plurality of capacitors each having a first terminal coupled to the first port, and also having a second terminal;

(b) a plurality of switches, each of the switches having a control electrode, a first main electrode, and a second main electrode, the first main electrode of each switch being coupled to the second port, the second main electrode of that switch being coupled to the second terminal of a corresponding one of the capacitors;

(c) a control circuit having a plurality of capacitance selection inputs representing the desired capacitance, a plurality of trim inputs representing a deviation from nominal of the capacitances of the capacitors, and a sign input, the control circuit producing a plurality of selection signals on the control electrodes of the plurality of switches, respectively, in response to the plurality of capacitance selection inputs in conjunction with the plurality of trim inputs and the sign input to select one or more of the switches and the capacitors coupled thereto to couple the selected capacitors in parallel between the first and second ports and thereby provide between the first and second ports an accurate value of the desired capacitance despite any deviations from nominal of the capacitances of the capacitors.

3. The integrated circuit capacitor array of claim 2 wherein the value of a digital code represented by the plurality of trim inputs represents the percentage deviation of the capacitance per unit area of the capacitors.

4. The integrated circuit capacitor array of claim 3 wherein the sign input represents an algebraic sign opposite to the polarity of the deviation of the capacitance per unit area of the capacitors.

5. The integrated circuit capacitor array of claim 4 wherein the plurality of capacitors are binarily weighted.

6. The integrated circuit capacitor array of claim 4 wherein the plurality of capacitance selection inputs are external inputs of an integrated circuit including the integrated circuit capacitor array to select one of a predetermined number of desired values of capacitance to appear between the first and second ports, each of the desired values corresponding to a different combination of logic states of the plurality of capacitance selection inputs.

7. The integrated circuit capacitor array of claim 6 wherein the plurality of trim inputs and the sign input are internal inputs of the integrated circuit and are settable during manufacture of the integrated circuit to couple a selectable combination of the capacitors in parallel.

8. The integrated circuit capacitor array of claim 7 including a plurality of circuits producing the plurality of trim inputs and the sign input, respectively, according to whether or not a link in each of the circuits is cut.

9. The integrated circuit array of claim 8 wherein each of the circuits includes a polycrystaline silicon resistor which causes the circuit to produce a "1" if the polycrystaline silicon resistor is cut through by a laser and a "0" if the polycrystaline silicon resistor is not cut.

10. The integrated circuit capacitor array of claim 5 wherein the control circuit produces the selection signals according to the expression

11. The integrated circuit capacitor array of claim 10 wherein the control circuit includes a stored look-up table of values of SEL corresponding to various combinations of values of the binary numbers CAPSEL, TRIM and TRS.

12. The integrated circuit capacitor array of claim 10 wherein the control circuit includes

i. a plurality of capacitance selection inputs, a plurality of trim inputs, and a sign input;

ii. a plurality of gates performing a logical ANDing function on various combinations of the capacitance selection inputs and the trim inputs;

iii. a first adder summing outputs of the ANDing function gates to produce a digital number representing a digital product of the capacitance selection inputs and the trim inputs;

iv. a circuit receiving the digital number and the sign input and performing an exclusive ORing function to combine the sign input with the digital number; and

v. a second adder which in accordance with the sign input effectively adds or subtracts the digital number to or from a digital number representing the capacitances selection inputs and the sign input to provide between the first and second ports an accurate value of the desired capacitance selected by the plurality of capacitance selection inputs.

13. An integrated circuit capacitor array having first and second ports and presenting a selectable desired capacitance between the first and second ports, comprising in combination:

(a) a plurality of capacitors each having a first terminal coupled to the first port and also having a second terminal;

(b) a plurality of switches, each of the switches having a control electrode, a first main electrode coupled to the second port, and a second main electrode coupled to the second terminal of a corresponding one of the capacitors, respectively;

(c) a control circuit including

i. a plurality of capacitance selection inputs, a plurality of trim inputs, and a sign input;

ii. a plurality of gates performing a logical ANDing function on various combinations of the capacitance selection inputs and the trim inputs;

iii. a first adder summing outputs of the ANDing function gates to produce a digital number representing a digital product of the capacitance selection inputs and the trim inputs;

iv. a circuit receiving the digital number and the sign input and performing an exclusive ORing function to combine the sign input with the digital number; and

v. a second adder which in accordance with the sign input effectively adds or subtracts the digital number to or from a digital number representing the capacitances selection inputs and the sign input to provide between the first and second ports an accurate value of the desired capacitance selected by the plurality of capacitance selection inputs despite deviations from nominal of the capacitance per unit area of the capacitors.

14. An integrated circuit current-to-voltage integrator, comprising in combination:

(a) an operational amplifier having an inverting input, a non-inverting input coupled to a reference voltage conductor, and an output;

(b) a capacitor array having first and second ports and presenting a selectable desired capacitance between the first and second ports, the first port being coupled to the inverting input and the second port being coupled to the output, the capacitor array including

i. a plurality of capacitors each having a first terminal coupled to the first port and also having a second terminal;

ii. a plurality of switches, each of the switches having a control electrode, a first main electrode coupled to the second port, and a second main electrode coupled to the second terminal of a corresponding one of the capacitors, respectively; and

iii. a control circuit having a plurality of capacitance selection inputs representing the desired capacitance, a plurality of trim inputs representing a deviation from nominal of the capacitances of the capacitors, and a sign input, the control circuit producing a plurality of selection signals on the control electrodes of the plurality of switches, respectively, in response to the plurality of capacitance selection inputs in conjunction with the plurality of trim inputs and the sign input to select one or more of the switches and the capacitors coupled thereto to couple the selected capacitors in parallel between the first and second ports and thereby provide between the first and second ports an accurate value of the desired capacitance despite any deviations from nominal of the capacitances of the capacitors.

15. A method of providing an accurate integrated circuit programmable capacitor array with a plurality of selectable values of capacitance between a first port and a second port despite manufacturing variations in the capacitance of individual capacitors in the array, the method comprising the steps of:

(a) providing in the array a plurality of capacitors each having a first terminal coupled to the first port, and also having a second terminal, and also providing a plurality of switches, each of the switches having a control electrode, a first main electrode, and a second main electrode, the first main electrode of each switch being coupled to the second port, the second main electrode of that switch being coupled to the second terminal of a corresponding one of the capacitors;

(b) obtaining a value representing a percentage deviation from nominal of the capacitors in the array;

(c) setting values of a plurality of trim inputs to represent the percentage deviation;

(d) setting values of a plurality of capacitance selection inputs to represent a predetermined value of desired capacitance between the first and second ports;

(e) in response to the capacitance selection inputs the trim inputs, producing a plurality of selection signals on the control electrodes of the plurality of switches, respectively, according to the expression;

space="preserve" listing-type="equation">SEL=K*CAPSEL+CAPSEL*TRIM,

wherein;

K is a scale factor equal to a ratio of a nominal user-selectable least significant bit capacitance divided by the minimum capacitance in the array,

CAPSEL is a binary number representing the logical states of the plurality of capacitance selection inputs, and

TRIM is a binary number representing the logical states of the plurality trim inputs.

16. The method of claim 15 wherein a sign input determines whether a number represented by the trim inputs is positive or negative.

17. The method of claim 16 wherein step (e) includes

i. performing a logical ANDing function on various combinations of the capacitance selection inputs and the trim inputs;

ii. summing outputs of the ANDing function to produce a digital number representing a digital product of the capacitance selection inputs and the trim inputs;

iii. performing an exclusive ORing function to combine the sign input with the digital number; and

iv. adding or subtracting the digital number to or from a digital number representing the capacitances selection inputs and the sign input to provide between the first and second ports an accurate value of the desired capacitance selected by the plurality of capacitance selection inputs.

18. A method of providing an accurate integrated circuit programmable capacitor array with a plurality of selectable values of capacitance between a first port and a second port despite manufacturing variations in the capacitance of individual capacitors in the array, the method comprising the steps of:

(a) providing in the array a plurality of capacitors each having a first terminal coupled to the first port, and also having a second terminal, and also providing a plurality of switches, each of the switches having a control electrode, a first main electrode, and a second main electrode, the first main electrode of each switch being coupled to the second port, the second main electrode of that switch being coupled to the second terminal of a corresponding one of the capacitors;

(b) obtaining a value representing a percentage deviation from nominal of the capacitors in the array;

(c) setting values of a plurality of trim inputs to represent the percentage deviation;

(d) setting values of a plurality of capacitance selection inputs to represent a predetermined value of desired capacitance between the first and second ports; and

(e) in response to the capacitance selection inputs and the trim inputs, producing a plurality of selection signals on the control electrodes of the plurality of switches.

19. The method of claim 18 wherein a sign input determines whether a number represented by the trim inputs is positive or negative.

20. The method of claim 19 wherein step (e) includes

i. performing a logical ANDing function on various combinations of the capacitance selection inputs and the trim inputs;

ii. summing outputs of the ANDing function to produce a digital number representing a digital product of the capacitance selection inputs and the trim inputs;

iii. performing an exclusive ORing function to combine the sign input with the digital number; and

iv. adding or subtracting the digital number to or from a digital number representing the capacitances selection inputs and the sign input to provide between the first and second ports an accurate value of the desired capacitance selected by the plurality of capacitance selection inputs.