Dithered sigma delta modulator having programmable full scale range adjustment

• US 5,905,453 A
• Filed: 08/04/1997
• Issued: 05/18/1999
• Est. Priority Date: 08/04/1997
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kase, Kiyoshi
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/905,700
• Time in Patent Office: 652 Days
• Field of Search: 341/131, 341/143, 341/139
• US Class Current: 341/143
• CPC Class Codes: H03M 3/332 in particular a pseudo-random signal
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/494 Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems

Abstract

A sigma delta modulator (10) for use in codec applications provides dynamic range adjustment and avoids asymmetrical signal clipping. The modulator (10) has a summing circuit that sums a plurality of inputs, one of which is a dither component. The dither is programmably modifiable to provide enhanced performance. The dither is provided by a pseudo random number generator (100). The pseudo random number generator (100) has an n-bit shift register (106) coupled to a last code detect (108) to detect the end of a pseudo random number sequence. At that time, a new preset code can be loaded (110) into the shift register (106) to provide different dither characteristics. This allows the pseudo random number generator (100) to programmably determine the percentage of ones and zeros to add to the output signal. The dither output can be inverted (104) to shift the dither up or down.

Claims

1. A sigma delta modulator comprising:

a summing circuit for summing a plurality of analog inputs; and

a modified pseudo random binary sequence generator for generating a dither component that is coupled to and provides one of the plurality of analog inputs to the summing circuit;

wherein the modified pseudo random binary sequence generator comprises;

a shift register comprising a sequenced plurality of bits with a first bit and a last bit, and an output polarity select circuit responsively coupled to an output

from the last bit and polarity select signal.

2. The sigma delta modulator in claim 1 wherein:

the output polarity select circuit has a polarity select input and a polarity select output;

the output polarity select circuit comprises an XOR gate with a first XOR input, a second XOR input, and an XOR output,

a first XOR input is the polarity select input,

the second XOR input is responsively coupled to the polarity select signal, and

the XOR output provides the polarity select output.

3. The sigma delta modulator in claim 1 wherein the modified pseudo random binary sequence generator further comprises:

a last code detector receiving values as inputs from each of the sequenced plurality of bits in the shift register and providing a last code detected signal.

4. The sigma delta modulator in claim 3 wherein:

a preset sequence is loaded into each of the sequenced plurality of bits in the shift register from a preset table entry in a preset value table upon receipt of the last code detected signal.

5. The sigma delta modulator in claim 4 wherein:

the preset value table is a table containing (2**n)-1 preset entries, wherein n is a number of the sequenced plurality of bits in the shift register.

6. The sigma delta modulator in claim 1 wherein:

the shift register contains seven shiftable bits.

7. The sigma delta modulator in claim 1 which further comprises:

a delay element responsively coupled to the summing circuit and providing one of the plurality of analog inputs to the summing circuit.

8. The sigma delta modulator of claim 1, wherein the modified pseudo random binary sequence generator further comprises:

an XNOR feedback loop comprising an XNOR gate with a first input connected to the output from the last bit, a second input connected to an output from the first bit, and an output that provides an input to the first bit.

9. The sigma delta modulator of claim 1, wherein the output from the last bit of the shift register is selectively inverted by the output polarity select circuit to produce the dither component.

10. A sigma delta modulator comprising:

a summing circuit for summing a plurality of analog inputs;

a delay element responsively coupled to the summing circuit and providing one of the plurality of analog inputs to the summing circuit; and

a modified pseudo random binary sequence generator for generating a dither component that is coupled to and provides one of the plurality of analog inputs to the summing circuit, wherein;

the modified pseudo random number generator comprises;

a shift register comprising a sequenced plurality of bits with a first bit and a last bit and containing seven shiftable bits,

an output polarity select circuit responsively coupled to an output from the last bit and a polarity select signal;

an XNOR feedback loop comprising an XNOR gate with a first input connected to the output from the last bit, a second input connected to an output from the first bit, and an output that provides an input to the first bit, and

a last code detector receiving values as inputs from each of the sequenced plurality of bits in the shift register and providing a last code detected signal,

the output polarity select circuit has a polarity select input and a polarity select output;

the output polarity select circuit comprises an XOR gate with a first XOR input, a second XOR input, and an XOR output,

a first XOR input is the polarity select input,

a second XOR input is responsively coupled to the polarity select signal,

the XOR output provides the polarity select output, and

a preset sequence is loaded into each of the sequenced plurality of bits in the shift register from a preset table entry in a preset value table upon receipt of the last code detected signal.

11. A method of converting an analog signal to a digital signal comprising:

receiving the analog signal as an input signal;

generating a dither signal that is programmably biasable; and

adding a plurality of signals including the analog signal and the dither signal to generate the digital signal;

wherein the step of generating the dither signal comprises;

sequentially shifting a plurality of bits through a shift register comprising an ordered plurality of bits, with a first bit and a last bit;

loading a preset pattern into the ordered plurality of bits, and

selectively inverting the dither signal based on a polarity select signal.

12. The method in claim 11 wherein:

the loading of a preset pattern is done from a specified preset table entry in a preset value table.

13. The method in claim 12 which further comprises:

selecting an entry in the preset value table as the specified preset table entry, and

selecting whether to assert or negate the polarity select signal.

14. The method in claim 11 wherein the step of generating the dither signal further comprises:

providing a bit to shift into the first bit of the shift register as a shift register input bit based on outputs from two of the ordered plurality of bits comprising the shift register;

shifting the shift register input bit into the first bit of the shift register.

15. The method in claim 14 wherein:

the providing a bit to shift into the first bit comprises;

XNORing an output from the first bit of the shift register with an output from the last bit of the shift register.

16. The method in claim 11 which further comprises:

testing each of the ordered plurality of bits for a specific pattern in order to generate a last code detected signal;

loading a preset pattern into the shift register in response to the last code detected signal.

17. The method in claim 11 which further comprises:

delaying an output signal from the adding, and wherein;

an output from the delaying is one of the plurality of added signals.

18. A method of converting an analog signal to a digital signal comprising:

receiving the analog signal as an input signal;

generating a dither signal that is programmably biasable, comprising;

sequentially shifting a plurality of bits through a shift register comprising an ordered plurality of bits, with a first bit and a last bit,

loading a preset pattern from a specified preset table entry in a preset value table into the ordered plurality of bits,

selectively inverting the dither signal based on a polarity select signal selecting an entry in the preset table as the specified preset table entry,

selecting whether to assert or negate the polarity select signal,

testing each of the ordered plurality of bits for a specific pattern in order to generate a last code detected signal, and

loading a preset pattern into the shift register in response to the last code detected signal; and

adding a plurality of signals including the analog signal and the dither signal to generate the digital signal.