Dithered sigma delta modulator having programmable full scale range adjustment
First Claim
1. A sigma delta modulator comprising:
- a summing circuit for summing a plurality of analog inputs; and
a modified pseudo random binary sequence generator for generating a dither component that is coupled to and provides one of the plurality of analog inputs to the summing circuit;
wherein the modified pseudo random binary sequence generator comprises;
a shift register comprising a sequenced plurality of bits with a first bit and a last bit, and an output polarity select circuit responsively coupled to an outputfrom the last bit and polarity select signal.
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Accused Products
Abstract
A sigma delta modulator (10) for use in codec applications provides dynamic range adjustment and avoids asymmetrical signal clipping. The modulator (10) has a summing circuit that sums a plurality of inputs, one of which is a dither component. The dither is programmably modifiable to provide enhanced performance. The dither is provided by a pseudo random number generator (100). The pseudo random number generator (100) has an n-bit shift register (106) coupled to a last code detect (108) to detect the end of a pseudo random number sequence. At that time, a new preset code can be loaded (110) into the shift register (106) to provide different dither characteristics. This allows the pseudo random number generator (100) to programmably determine the percentage of ones and zeros to add to the output signal. The dither output can be inverted (104) to shift the dither up or down.
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Citations
18 Claims
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1. A sigma delta modulator comprising:
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a summing circuit for summing a plurality of analog inputs; and a modified pseudo random binary sequence generator for generating a dither component that is coupled to and provides one of the plurality of analog inputs to the summing circuit; wherein the modified pseudo random binary sequence generator comprises; a shift register comprising a sequenced plurality of bits with a first bit and a last bit, and an output polarity select circuit responsively coupled to an output from the last bit and polarity select signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A sigma delta modulator comprising:
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a summing circuit for summing a plurality of analog inputs; a delay element responsively coupled to the summing circuit and providing one of the plurality of analog inputs to the summing circuit; and a modified pseudo random binary sequence generator for generating a dither component that is coupled to and provides one of the plurality of analog inputs to the summing circuit, wherein; the modified pseudo random number generator comprises; a shift register comprising a sequenced plurality of bits with a first bit and a last bit and containing seven shiftable bits, an output polarity select circuit responsively coupled to an output from the last bit and a polarity select signal; an XNOR feedback loop comprising an XNOR gate with a first input connected to the output from the last bit, a second input connected to an output from the first bit, and an output that provides an input to the first bit, and a last code detector receiving values as inputs from each of the sequenced plurality of bits in the shift register and providing a last code detected signal, the output polarity select circuit has a polarity select input and a polarity select output; the output polarity select circuit comprises an XOR gate with a first XOR input, a second XOR input, and an XOR output, a first XOR input is the polarity select input, a second XOR input is responsively coupled to the polarity select signal, the XOR output provides the polarity select output, and a preset sequence is loaded into each of the sequenced plurality of bits in the shift register from a preset table entry in a preset value table upon receipt of the last code detected signal.
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11. A method of converting an analog signal to a digital signal comprising:
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receiving the analog signal as an input signal; generating a dither signal that is programmably biasable; and adding a plurality of signals including the analog signal and the dither signal to generate the digital signal; wherein the step of generating the dither signal comprises; sequentially shifting a plurality of bits through a shift register comprising an ordered plurality of bits, with a first bit and a last bit; loading a preset pattern into the ordered plurality of bits, and selectively inverting the dither signal based on a polarity select signal. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method of converting an analog signal to a digital signal comprising:
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receiving the analog signal as an input signal; generating a dither signal that is programmably biasable, comprising; sequentially shifting a plurality of bits through a shift register comprising an ordered plurality of bits, with a first bit and a last bit, loading a preset pattern from a specified preset table entry in a preset value table into the ordered plurality of bits, selectively inverting the dither signal based on a polarity select signal selecting an entry in the preset table as the specified preset table entry, selecting whether to assert or negate the polarity select signal, testing each of the ordered plurality of bits for a specific pattern in order to generate a last code detected signal, and loading a preset pattern into the shift register in response to the last code detected signal; and adding a plurality of signals including the analog signal and the dither signal to generate the digital signal.
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Specification