Accelerated Graphics Port two level Gart cache having distributed first level caches

• US 5,905,509 A
• Filed: 09/30/1997
• Issued: 05/18/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Chin, Kenneth Tom, Lester, Robert Allan, Jones, Phillip M.
• Primary Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/941,860
• Time in Patent Office: 595 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/512, 345/508, 345/511, 345/203, 711/100, 711/117-122, 711/141-143, 711/200, 711/202, 711/203, 711/205-209, 711/221, 395/309, 395/310, 395/280, 395/284, 395/728, 395/729, 395/731, 395/828, 395/829, 395/842, 395/843, 395/846-848, 395/859, 395/872, 395/874
• US Class Current: 345/520
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset caches a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. The core logic chipset uses a two-level GART cache comprising a plurality of first-level GART caches and a common second level GART cache. Each of the plurality of first-level GART caches are coupled to a respective interface in the computer system and effectively de-couple the different interface GART address translations so that GART cache thrashing and cache arbitration delays are substantially reduced. Separate decoupled first-level GART caches for each interface allow concurrent GART address translations among the different interfaces. Individual first-level GART caches may be fined tuned for each associated interface.

Claims

1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) processor, said system comprising:

a system processor executing software instructions and generating graphics data;

a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;

the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;

an accelerated graphics port (AGP) processor generating video display data from the graphics data and adapted for connection to a video display to display the video display data;

a core logic chipset having a common second-level cache memory;

said core logic chipset having a first interface logic for connecting said system processor to said system memory;

said first interface logic having a first first-level cache memory, said first first-level cache memory connected to said common second-level cache memory;

said core logic chipset having a second interface logic for connecting said system processor and said system memory to said AGP processor;

said second interface logic having a second first-level cache memory, said second first-level cache memory connected to said common second-level cache memory;

a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding system memory address of each of the plurality of pages of graphics data, the plurality of GART table entries being stored in some other of the plurality of bytes of storage of said system memory and each of the plurality of GART table entries being associated with a block of graphics device addresses;

said AGP processor requests a graphics data transaction by asserting a graphics device address to said second interface logic; and

said second interface logic determines if a required one of the plurality of GART table entries is stored in said second first-level cache memory, wherein;

if the required one of the plurality of GART table entries is stored in said second first-level cache memory then said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to a corresponding address of a one of the plurality of pages of graphics data stored in said system memory;

if the required one of the plurality of GART table entries is not stored in said second first-level cache memory, then said core logic chipset determines if the required one of the plurality of GART table entries is stored in said common second-level cache memory;

if the required one of the plurality of GART table entries is stored in said common second-level cache memory, then said core logic chipset stores the required one in said second first-level cache memory, and said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory; and

if the required one of the plurality of GART table entries is not stored in said common second-level cache memory, then said core logic chipset accesses said system memory to obtain the required one of the plurality of GART table entries from said GART table, said core logic chipset stores the required one of the plurality of GART table entries from said GART table in said common second-level cache memory and said second first-level cache memory, and said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory.

2. The computer system of claim 1, wherein:

said system processor requests a graphics data transaction by asserting a graphics device address to said first interface logic; and

said first interface logic determines if a required one of the plurality of GART table entries is stored in said first first-level cache memory, wherein;

if the required one of the plurality of GART table entries is stored in said first first-level cache memory, then said first interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to a corresponding address of a one of the plurality of pages of graphics data stored in said system memory;

if the required one of the plurality of GART table entries is not stored in said first first-level cache memory, then said core logic chipset determines if the required one of the plurality of GART table entries is stored in said common second-level cache memory;

if the required one of the plurality of GART table entries is stored in said common second-level cache memory, then said core logic chipset stores the required one in said first first-level cache memory, and said first interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory; and

if the required one of the plurality of GART table entries is not stored in said common second-level cache memory, then said core logic chipset accesses said system memory to obtain the required one of the plurality of GART table entries from said GART table, said core logic chipset stores the required one of the plurality of GART table entries from said GART table in said common second-level cache memory and said first first-level cache memory, and said first interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory.

3. The computer system of claim 1, further comprising:

a third interface logic for connecting said system processor and said system memory to input-output devices;

said third interface logic having a third first-level cache memory, said third first-level cache memory connected to said common second-level cache memory;

a one of said input-output devices requests a graphics data transaction by asserting a graphics device address to said third interface logic, and

said third interface logic determines if a required one of the plurality of GART table entries is stored in said third first-level cache memory, wherein;

if the required one of the plurality of GART table entries is stored in said third first-level cache memory, then said third interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to a corresponding address of a one of the plurality of pages of graphics data stored in said system memory;

if the required one of the plurality of GART table entries is not stored in said third first-level cache memory, then said core logic chipset determines if the required one of the plurality of GART table entries is stored in said common second-level cache memory;

if the required one of the plurality of GART table entries is stored in said common second-level cache memory, then said core logic chipset stores the required one in said third first-level cache memory, and said third interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory; and

if the required one of the plurality of GART table entries is not stored in said common second-level cache memory, then said core logic chipset accesses said system memory to obtain the required one of the plurality of GART table entries from said GART table, said core logic chipset stores the required one of the plurality of GART table entries from said GART table in said common second-level cache memory and said third first-level cache memory, and said third interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory.

4. The computer system of claim 1, further comprising a fourth interface logic for connecting said system processor and said system memory to storage devices.

5. The computer system of claim 1, wherein the plurality of pages of GART table entries are stored in said system memory in a non-contiguous and random order.

6. The computer system of claim 1, further comprising a GART directory having a plurality of entries, each of the plurality of GART directory entries comprising an address pointer to a corresponding one of the plurality of pages of GART table entries, wherein the plurality of GART directory entries are used for locating the plurality of pages of GART table entries in said system memory.

7. The computer system of claim 6, wherein said common second-level cache memory stores selected ones of the plurality of GART directory entries.

8. The computer system of claim 6, wherein said first first-level cache memory stores selected ones of the plurality of GART directory entries.

9. The computer system of claim 6, wherein said second first-level cache memory stores selected ones of the plurality of GART directory entries.

10. The computer system of claim 1, wherein said common second-level cache memory is a direct mapped cache memory.

11. The computer system of claim 1, wherein said common second-level cache memory is a multi-way cache memory.

12. The computer system of claim 1, wherein said common second-level cache memory is a four-way cache memory.

13. The computer system of claim 1, wherein said first first-level cache memory is a direct mapped cache memory.

14. The computer system of claim 1, wherein said first first-level cache memory is a multi-way cache memory.

15. The computer system of claim 1, wherein said first first-level cache memory comprises separate read and write cache memories.

16. The computer system of claim 1, wherein said second first-level cache memory is a direct mapped cache memory.

17. The computer system of claim 1, wherein said second first-level cache memory is a multi-way cache memory.

18. The computer system of claim 1, wherein:

said first and second first-level cache memories are connected to said common second-level cache memory with a multiplexer; and

said multiplexer selects said first and second first-level cache memories with a cache arbiter.

19. The computer system of claim 1, wherein the number of the plurality of bytes of storage in each of the plurality of pages of graphics data is 4096 bytes.

20. The computer system of claim 1, wherein the system processor is a plurality of system processors.

21. The computer system of claim 1, further comprising a video display.

22. The computer system of claim 1, wherein the plurality of pages of graphics data are stored in said random access memory in a non-contiguous and random order.

23. The computer system of claim 1, further comprising a network interface card, a hard disk, a floppy disk drive, a modem, a keyboard and a mouse.

24. The computer system of claim 1, further comprising a serial port, a parallel port and a real time clock.

25. The computer system of claim 1, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

26. The computer system of claim 1, wherein said core logic chipset is at least one integrated circuit.

27. The computer system of claim 26, wherein said at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

28. The computer system of claim 26, wherein said at least one integrated circuit core logic chipset is at least one programmable logic array integrated circuit.

29. A core logic chipset adapted for connection to a computer system processor and system memory, and an accelerated graphics port (AGP), comprising:

an accelerated graphics port (AGP) interface having AGP request and reply queues, an AGP data and control logic, an AGP arbiter, and an AGP first-level graphics address remapping table (GART) cache, said AGP interface adapted for connection to an AGP processor,

a processor interface having, processor address queues and processor data queues, a processor data and control logic, and a processor first-level GART cache, said processor interface adapted for connection to a computer system processor;

a memory interface and control logic adapted for connecting to a computer system memory; and

a common second-level GART cache, said common second-level GART cache connected to said processor and AGP first-level GART caches, and said memory interface and control logic;

said AGP interface is adapted for receiving a graphics data transaction, such that said AGP interface determines if a required one of a plurality of GART table entries is stored in said AGP first-level GART cache, wherein;

if the required one of the plurality of GART table entries is stored in said AGP first-level GART cache, then said AGP interface uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to a corresponding address of a one of the plurality of pages of graphics data stored in the computer system memory;

if the required one of the plurality of GART table entries is not stored in said AGP first-level GART cache, then said core logic chipset determines if the required one of the plurality of GART table entries is stored in said common second-level GART cache;

if the required one of the plurality of GART table entries is stored in said common second-level GART cache, then said core logic chipset stores the required one in said AGP first-level GART cache, and said AGP interface uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in the computer system memory; and

if the required one of the plurality of GART table entries is not stored in said common second-level GART cache, then said core logic chipset is adapted to access the computer system memory to obtain the required one of the plurality of GART table entries from a GART table, said core logic chipset is adapted to store the required one of the plurality of GART table entries from the GART in said common second-level GART cache and said AGP second first-level GART cache, and said AGP interface uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory.

30. The core logic chipset of claim 29, wherein said AGP first-level GART cache is a multi-way cache memory.

31. The core logic chipset of claim 29, wherein said processor first-level GART cache is a direct mapped cache memory comprising separate read and write caches.

32. The core logic chipset of claim 29, wherein said common second-level GART cache is a multi-way cache memory.

33. The core logic chipset of claim 29, wherein said common second-level GART cache is a direct mapped cache memory.

34. The core logic chipset of claim 29, wherein:

said AGP and processor first-level GART caches are connected to said common second-level GART cache with a multiplexer; and

said multiplexer selects said AGP and processor first-level GART caches with a cache arbiter.