Separable cells having wiring channels for routing signals between surrounding cells

• US 5,905,655 A
• Filed: 06/09/1997
• Issued: 05/18/1999
• Est. Priority Date: 08/24/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Deeley, Richard
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/871,212
• Time in Patent Office: 708 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 326/41, 326/47, 326/101
• US Class Current: 716/131
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e.g., timing constraints) will be met. A plurality of surrounding cells may be interconnected by routing their signals in stacked wiring layers. The megacell may be split or stretched about two or more parting lines to create two or more wiring channels.

Claims

1. A method of designing an integrated circuit, comprising:

providing a separable cell;

providing at least two additional cells;

separating said separable cell into two or more sub-blocks to provide a channel between an adjacent pair of said two or more sub-blocks; and

forming an external interconnect line through said channel, said external interconnect line interconnecting said at least two additional cells.

2. The method of claim 1, further comprising interconnecting across said channel from one said sub-block to another said sub-block with an internal interconnect line.

3. The method of claim 2, wherein said channel accommodates said external and internal interconnect lines in tuples.

4. The method of claim 1, wherein said separable cell is separated about a plurality of parting lines.

5. The method of claim 4, wherein at least two of said parting lines are non-parallel.

6. An integrated circuit comprising:

a plurality of cells;

a separable cell between said plurality of cells, said separable cell separated into two or more sub-blocks in a manner that forms a channel between an adjacent pair of said two or more sub-blocks; and

an interconnect line formed through said channel, wherein at least two of said plurality of cells are interconnected through said interconnect line.

7. An integrated circuit comprising:

a separable cell separated into two or more sub-blocks in a manner that forms a channel;

a plurality of additional cells; and

an interconnect line formed through said channel, interconnecting at least two of said plurality of additional cells.

8. The integrated circuit of claim 7, wherein said separable cell is a megacell.

9. The integrated circuit of claim 7, wherein said plurality of additional cells are standard cells.

10. The integrated circuit of claim 7, wherein said separable cell is between said at least two of said plurality of additional cells.

11. The integrated circuit of claim 7, wherein said separable cell is adjacent to said at least two of said plurality of additional cells.

12. The integrated circuit of claim 7, wherein said channel does not include at least a portion of said two or more sub-blocks.

13. The integrated circuit of claim 7, wherein said interconnect line is an external interconnect line and passes through said channel from one of said plurality of additional cells to another of said plurality of additional cells, and said integrated circuit further comprises an internal interconnect line passing across said channel from one said sub-block to another said sub-block.

14. The integrated circuit of claim 13, wherein said channel accommodates said internal interconnect line and said external interconnect line in tuples.

15. The integrated circuit of claim 7, wherein said separable cell is separated about a plurality of parting lines.

16. The integrated circuit of claim 15, wherein said plurality of parting lines are parallel.

17. The integrated circuit of claim 15, wherein at least two of said plurality of parting lines are non-parallel.

18. The integrated circuit of claim 7, wherein the total size of said two or more sub-blocks and said channel is larger than the size of said separable cell prior to being separated.