Digital processing system for binary addition/subtraction

• US 5,905,662 A
• Filed: 09/11/1997
• Issued: 05/18/1999
• Est. Priority Date: 09/13/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiraishi, Mikio
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/927,210
• Time in Patent Office: 614 Days
• Field of Search: 364/745.03, 364/748.04, 364/737
• US Class Current: 708/552
• CPC Class Codes: G06F 7/4991 Overflow or underflow
• CPC Class Codes: G06F 7/505 in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

Abstract

A digital processing system for binary addition/subtraction includes an adder for adding two binary data respectively expressed by two'"'"'s complements to output the addition result, an overflow carry detector for outputting an overflow carry signal indicating an overflow carry of the addition result, an exclusive OR gate for outputting the sign bit of the addition result of the adder with or without inversion, and a register for storing the output from the exclusive OR gate.

Claims

1. A digital processing system comprising:

arithmetic operation means for adding two binary data respectively having sign bits to output an arithmetic operation result having a sign bit;

overflow carry detection means, connected to said arithmetic operation means, for outputting an overflow carry signal indicating an overflow carry of the arithmetic operation result on the basis of contents of the respective sign bits of the two binary data and the arithmetic operation result; and

sign bit output means, connected to said overflow carry detection means, for outputting a sign flag with or without inverting the sign bit of the addition result in accordance with contents of the overflow carry signal.

2. A system according to claim 1, further comprising an overflow carry signal register connected to said sign bit output means to store the overflow carry signal.

3. A system according to claim 2, further comprising a sign flag register connected to said sign bit output means to store the sign flag, and to output stored contents as an absolute sign flag.

4. A system according to claim 3, further comprising an accumulator connected to said arithmetic operation means to store the addition result, and to output stored contents as an arithmetic operation result.

5. A system according to claim 4, further comprising a bit shifter, connected to said sign flag register and said accumulator, for supplying bit shift data having the arithmetic operation result without any change or having the absolute sign flag as the most significant bit and the arithmetic operation result as a lower bit.

6. A system according to claim 5, wherein said bit shifter includes

circuit means for generating bit shift data having the absolute sign flag as the most significant bit and the arithmetic operation result as a lower bit when a control input corresponding to the overflow carry signal from said overflow carry detection means indicates an overflow carry state, and for generating bit shift data corresponding to the arithmetic operation result itself when the control input corresponding to the overflow carry signal from said overflow carry detection means does not indicate the overflow carry state.

7. A system according to claim 1, further comprising a sign flag register connected to said sign bit output means to store the sign flag, and to output stored contents as an absolute sign flag.

8. A system according to claim 7, further comprising an accumulator connected to said arithmetic operation means to store the addition result, and to output stored contents as an arithmetic operation result.

9. A system according to claim 8, further comprising a bit shifter, connected to said sign flag register and said accumulator, for supplying bit shift data having the arithmetic operation result without any change or having the absolute sign flag as the most significant bit and the arithmetic operation result as a lower bit.

10. A system according to claim 9, wherein said bit shifter includes

circuit means for generating bit shift data having the absolute sign flag as the most significant bit and the arithmetic operation result as a lower bit when a control input corresponding to the overflow carry signal from said overflow carry detection means indicates an overflow carry state, and for generating bit shift data corresponding to the arithmetic operation result itself when the control input corresponding to the overflow carry signal from said overflow carry detection means does not indicate the overflow carry state.

11. A system according to claim 1, wherein said arithmetic operation means includes a program memory storing a predetermined arithmetic operation procedure as a program, and

a decoder for reading out the program from said program memory, and decoding contents of the program to generate a decoding result and a carry signal.

12. A system according to claim 11, wherein said arithmetic operation means includes selective inverter means for performing, in accordance with contents of the decoding result from said decoder, any of an operation of outputting one of the binary data without any change, an operation of outputting one of the binary data upon inverting a logic level of one binary data, and an operation of outputting no data.

13. A system according to claim 12, wherein said arithmetic operation means includes an adder which receives the carry signal from said decoder, the other of the binary data, and an output from said selective inverter means, for adding the two binary data.

14. A system according to claim 13, wherein, when "a" represents the sign bit of the other of the binary data, "b" represents a sign bit of an output from said selective inverter means, and "m" represents the sign bit of the addition result from said arithmetic operation means, said overflow carry detection means includes

coincidence detection means for detecting a coincidence state "a=b" to generate a coincidence detection result,

noncoincidence detection means for detecting a noncoincidence state "b≠

m" to generate a noncoincidence detection result, and

means, connected to said coincidence detection means and said noncoincidence detection means, for outputting the overflow carry signal when the states "a=b" and "b≠

m" are detected.

15. A system according to claim 12, wherein, when "a" represents the sign bit of the other of the binary data, "b" represents a sign bit of an output from said selective inverter means, and "m" represents the sign bit of the addition result from said arithmetic operation means, said overflow carry detection means includes

coincidence detection means for detecting a coincidence state "a=b" to generate a coincidence detection result,

noncoincidence detection means for detecting a noncoincidence state "b≠

m" to generate a noncoincidence detection result, and

means, connected to said coincidence detection means and said noncoincidence detection means, for outputting the overflow carry signal when the states "a=b" and "b≠

m" are detected.

16. A system according to claim 1, wherein at least one of the two binary data includes binary data expressed by a two'"'"'s complement.

17. A digital processor comprising:

first means for storing first binary data constituted by a plurality of bits having a first sign bit, and outputting the first binary data;

second means for selectively performing any of a direct output of second binary data and an output of third binary data corresponding to the second binary data, said second binary data being constituted by a plurality of bits having a second sign bit, and said third binary data being obtained by inverting levels of all bits of the second binary data and being constituted by a plurality of bits having a third sign bit corresponding to the second sign bit;

third means for adding the first binary data from said first means and the second binary data from said second means so as to output an addition result constituted by a plurality of bits having a fourth sign bit;

fourth means, connected to said first, second, and third means, for outputting an overflow carry signal indicating an overflow carry of the addition result on the basis of contents of the first, second, and fourth sign bits; and

fifth means, connected to said fourth means, for outputting a sign flag with or without inverting the fourth sign bit of the addition result in accordance with contents of the overflow carry signal.

18. A processor according to claim 17, further comprising sixth means, connected to said fifth means, for storing the sign flag, and outputting stored contents as an absolute sign flag.

19. A processor according to claim 18, further comprising seventh means, connected to said third means, for storing the addition result, and outputting stored contents as an arithmetic operation result.

20. A processor according to claim 19, further comprising eighth means, connected to said sixth means and said seventh means, for supplying bit shift data having the arithmetic operation result without any change or having the absolute sign flag as the most significant bit and the arithmetic operation result as a lower bit.

21. A processor according to claim 20, wherein said eighth means includes

circuit means for generating bit shift data having the absolute sign flag as the most significant bit and the arithmetic operation result as a lower bit when a control input corresponding to the overflow carry signal from said fourth means indicates an overflow carry state, and for generating bit shift data corresponding to the arithmetic operation result itself when the control input corresponding to the overflow carry signal from said fourth means does not indicate the overflow carry state.