Modulo address generating circuit and method with reduced area and delay using low speed adders

• US 5,905,665 A
• Filed: 08/05/1997
• Issued: 05/18/1999
• Est. Priority Date: 01/10/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Rim, Min-Joong
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/906,273
• Time in Patent Office: 651 Days
• Field of Search: 364/746, 364/768, 364/769, 364/715.06, 340/146.2
• US Class Current: 708/491
• CPC Class Codes: G06F 2205/106 Details of pointers, i.e. structure of the address generators
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06F 7/72 using residue arithmetic
• CPC Class Codes: G06F 9/3552 using wraparound, e.g. modulo or circular addressing

Abstract

A modulo address generating apparatus and method are disclosed which obtain high speed performance with reduced integrated circuit area. A modulo address generator according to the present invention includes a first adder for adding a current address to an address increment to generate an incremented address, an inverter for producing a complement of a maximum address, a second adder for generating a circular correction value by adding the complement of the maximum address to a minimum address, an adder/subtracter for generating a corrected next address by adding or subtracting the circular correction value to or from the incremented address according to a sign value of the address increment, a comparator for checking whether the incremented address is within an address range defined by the maximum and minimum addresses, and a multiplexor controlled by the comparator which selects the incremented address for output as a next address when the incremented address is within the address range and selects the corrected address for output as the next address when the incremented address is outside the address range.

Claims

1. A modulo address generator comprising:

a first adder configured to receive a current address value and an address increment value and add the current address value and the address increment value to generate an incremented address value;

an inverter configured to receive a maximum address value of a data region and generate a complemented maximum address value;

a second adder configured to receive the complemented maximum address value and a minimum address value of the data region and add the complemented maximum address value and the minimum address value to generate a circular correction value;

an adder/subtracter configured to receive the incremented address value, the circular correction value and a sign bit of the address increment value, wherein the adder/subtracter is further configured to add the incremented address value and the circular correction value responsive to a positive value of the sign bit and subtract the circular correction value from the incremented address value responsive to a negative value of the sign bit in order to generate a corrected address value;

a comparator configured to receive the incremented address value, determine whether the incremented address value is within an address range defined by the maximum and minimum addresses, and generate a selection signal having a first logic value when the incremented address value is within the address range and a second logic value when the incremented address value is outside the address range; and

a multiplexor configured to receive the incremented address value, the corrected address value and the selection signal, wherein the multiplexor is further configured to select the incremented address value for output as a next address responsive to the first logic value of the selection signal and select the corrected address value for output as the next address responsive to the second logic value of the selection signal.

2. The modulo address generator of claim 1, wherein the first and second adders are low-speed adders.

3. The modulo address generator of claim 1, wherein the adder/subtracter is a low-speed adder/subtracter.

4. A modulo address generating method comprising the steps of:

generating an incremented address value by adding a current address to an address increment;

generating a circular correction value by adding a complement of a maximum address of a data region to a minimum address of the data region;

generating a corrected address value by subtracting the circular correction value from the incremented address value when a sign bit of the address increment is a first logic level and adding the circular correction value to the incremented address value when the sign bit is a second logic level;

comparing the incremented address value to an address range defined by the maximum address and minimum address to generate a selection signal; and

selecting the incremented address value as a next address value when the incremented address value is within the address range and selecting the corrected address value as the next address value when the incremented address is outside the address range.