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Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system

  • US 5,905,998 A
  • Filed: 05/19/1997
  • Issued: 05/18/1999
  • Est. Priority Date: 03/31/1995
  • Status: Expired due to Term
First Claim
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1. A computer system, comprising:

  • a system controller;

    a multiplicity of sub-systems coupled to the system controller;

    a main memory coupled to the system controller; and

    a plurality of the sub-systems comprising data processors, a plurality of the data processors each having a respective cache memory that stores multiple blocks of data and a respective set of cache tags, including one cache tag for each data block stored by the cache memory;

    each of the plurality of data processors including an interface, coupled to the system controller, for sending memory transaction requests to the system controller;

    the interface for each of the data processors that has a cache memory including circuitry for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors;

    each memory transaction request having an associated address value;

    the system controller including;

    transaction activation logic for activating each memory transaction request when it meets predefined activation criteria, and for blocking each memory transaction request until the predefined activation criteria are met;

    wherein the predefined activation criteria include an address conflict criterion that is a function of the address value associated with the memory transaction request and the address value of activated memory transaction requests;

    an active transaction status table that stores active transaction status data representing memory transaction requests which have been activated by the transaction activation logic, the active transaction status data including data for each activated transaction representing an address value associated with the transaction;

    the active transaction status data including data representing memory transaction requests received from the plurality of data processors; and

    memory transaction request logic for processing the memory transaction request after it has been activated by the transaction activation logic;

    the transaction activation logic including parallel comparison logic for simultaneously comparing one not-yet-activated memory transaction request with the stored active transaction status data for all activated memory transaction requests so as to detect whether activation of the each memory transaction request would violate the predefined activation criteria with respect to any of the activated memory transaction requests;

    wherein the transaction activation logic blocks all transaction requests by any of the data processors that violate the predefined activation criteria with respect to any memory transaction that has already been activated.

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