Computer with a cache controller and cache memory with a priority table and priority levels

• US 5,906,000 A
• Filed: 02/18/1997
• Issued: 05/18/1999
• Est. Priority Date: 03/01/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Abe, Yuichi, Matoba, Tsukasa
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US08/802,840
• Time in Patent Office: 819 Days
• Field of Search: 711/160, 711/136, 711/151, 711/147, 711/159, 711/133, 711/135, 711/134, 711/117, 711/118
• US Class Current: 711/151
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A computer system according to the present invention comprises a processor, a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority corresponding to the frequency of access by the processor to read each of the data items, a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority corresponding to each of the data items, and a controller including means for obtaining, when a cache miss has occurred, a priority corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor, and means for comparing the obtained priority with a priority of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.

Claims

1. A computer system comprising:

a processor;

a priority table for storing an address indicative of the original location of each data items to be read by the processor and a priority level corresponding to the frequency of access by the processor to read each of the data items;

a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority level corresponding to each of the data items; and

a controller including;

means for obtaining, when a cache miss has occurred, a priority level corresponding to data requested by the processor, by referring to the priority table and using an address included in the request of the processor, and

means for comparing the obtained priority level with a priority level of data stored in a predetermined cache block in the cache memory, thereby to determine whether data replacement should be performed in the predetermined cache block.

2. The computer system according to claim 1, wherein the determination means determines to perform replacement of data when the obtained priority level is higher than the priority level of data prestored in the cache block.

3. The computer system according to claim 2, wherein the controller includes a replacement executing means for erasing data in the predetermined cache block, writing into the predetermined cache block the data whose reading is requested by the processor, and writing the priority level of the data into the tag, when data replacement is determined to be performed.

4. The computer system according to claim 1, wherein the determination means determines not to perform replacement of data when the priority level of data prestored in the cache block is higher than the obtained priority level.

5. The computer system according to claim 4, wherein the controller has means for reducing, by a predetermined degree, a priority level stored in the tag and corresponding to the data when data replacement is determined not to be performed.

6. The computer system according to claim 4, wherein the controller has means for reducing, by a degree of 1, a priority level stored in the tag and corresponding to the data when data replacement is determined not to be performed.

7. The computer system according to claim 1, wherein the controller has means for writing, into an empty cache block if there is any, the data whose reading is requested by the processor, and writing the priority level of the data into the tag.

8. The computer system according to claim 1, wherein the priority table is incorporated in the controller.

18. The computer system according to claim 1, wherein the priority level in the priority table is predetermined.

19. The computer system according to claim 1, wherein the priority level is expressed by a numerical value of one byte.

9. A computer system comprising:

a processor;

a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority level corresponding to the frequency of access by the processor to read each of the data items;

a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority level corresponding to each of the data items; and

a controller including;

means for obtaining, when a cache miss has occurred, a priority level corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor,

means for comparing the obtained priority level with a priority level of data stored in a predetermined cache block in the cache memory,

means for determining to perform replacement of data when the obtained priority level is higher than the priority level of data prestored in the cache block,

replacement executing means for erasing data in the predetermined cache block, writing into the predetermined cache block the data requested by the processor, and writing the priority level of the data into the tag, when data replacement is determined to be performed,

means for determining not to perform replacement of data when the priority level of data prestored in the cache block is higher than the obtained priority level, and

means for reducing, by a predetermined degree, a priority level stored in the tag and corresponding to the data when data replacement is determined not to be performed.

10. A cache memory control method for use in a computer system having a processor and a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, comprising the steps of:

providing a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority level corresponding to the frequency of access by the processor to read each of the data items;

storing, in a tag in the cache memory, an address and a priority level corresponding to each of the data items;

obtaining, when a cache miss has occurred, a priority level corresponding to data requested by the processor, by referring to the priority table and using an address included in the request of the processor; and

comparing the obtained priority level with a priority level of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.

11. The method according to claim 10, wherein in the determination step, it is determined to perform replacement of data when the obtained priority level is higher than the priority level of data prestored in the cache block.

12. The method according to claim 11, further comprising the step of erasing data in the predetermined cache block, writing into the predetermined cache block the data whose reading is requested by the processor, and writing the priority level of the data into the tag, when data replacement is determined to be performed.

13. The method according to claim 10, wherein in the determination step, it is determined not to perform replacement of data when the priority level of data prestored in the cache block is higher than the obtained priority level.

14. The method according to claim 13, further comprising the step of reducing, by a predetermined degree, a priority level stored in the tag and corresponding to the data when data replacement is determined not to be performed.

15. The method according to claim 13, further comprising the step of reducing, by a degree of 1, a priority level stored in the tag and corresponding to the data when data replacement is determined not to be performed.

16. The method according to claim 10, further comprising writing, into an empty cache block if there is any, the data whose reading is requested by the processor, and writing the priority level of the data into the tag.

20. The method according to claim 10, wherein the priority level in the priority table is predetermined.

21. The method according to claim 10, wherein the priority level is expressed by a numerical value of one byte.

17. A cache memory control method for use in computer system having a processor and a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, comprising the steps of:

providing a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority level corresponding to the frequency of access by the processor to read each of the data items;

storing, in a tag in the cache memory, an address and a priority level corresponding to each of the data items;

obtaining, when a cache miss has occurred, a priority level corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor;

comparing the obtained priority level with a priority level of data stored in a predetermined cache block in the cache memory;

determining to perform replacement of data when the obtained priority is higher than the priority level of data prestored in the cache block;

erasing data in the predetermined cache block, writing into the predetermined cache block the data requested by the processor, and writing the priority level of the data into the tag, when data replacement is determined to be performed;

determining not to perform replacement of data when the priority level of data prestored in the cache block is higher than the obtained priority level; and

reducing, by a predetermined degree, a priority level stored in the tag and corresponding to the data when data replacement is determined not to be performed.

22. A computer system comprising:

a processor;

a priority table for storing an address indicative of the original location of each data items to be read by the processor and a priority level corresponding to the frequency of access by the processor to read each of the data items;

a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority level corresponding to each of the data items; and

a controller including;

means for obtaining, when a cache miss has occurred, a priority level corresponding to data requested by the processor, by referring to the priority table and using an address included in the request of the processor;

means for comparing the obtained priority level with a priority level of data stored in a predetermined cache block in the cache memory;

means for determining whether the data replacement should be performed in the predetermined cache block; and

means for reducing, by a degree of one, a priority level stored in the tag corresponding to the data when the priority level of data prestored in the cache block is higher than the obtained priority level data.

23. A cache memory control method for use in a computer system having a processor and a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, comprising the steps of:

providing a priority table for storing an address indicative of the original location of each data item to be read by the processor, and a priority level corresponding to the frequency of access by the processor to read each of the data items;

storing, in a tag in the cache memory, an address and a priority level corresponding to each of the data items;

obtaining, when a cache miss has occurred, a priority level corresponding to data requested by the processor, by referring to the priority table and using an address included in the request of the processor;

comparing the obtained priority level with a priority level of data stored in a predetermined cache block in the cache memory;

determining whether the data replacement should be performed in the predetermined cache block; and

reducing, by a degree of one, a priority level stored in the tag corresponding to the data when the priority level of data prestored in the cache block is higher than the obtained priority level data.