Silicon-germanium-carbon compositions in selective etch processes

• US 5,906,708 A
• Filed: 12/06/1995
• Issued: 05/25/1999
• Est. Priority Date: 11/10/1994
• Status: Expired due to Fees

• Current Assignee: Lawrence Semiconductor Research Laboratory, Inc. (Entegris Incorporated)
• Original Assignee: Lawrence Semiconductor Research Laboratory, Inc. (Entegris Incorporated)
• Inventors: Hunt, Charles E., Robinson, McDonald, Westhoff, Richard C., Ling, Li
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/567,971
• Time in Patent Office: 1,266 Days
• Field of Search: 437/965, 437/974, 437/228, 156/657.1, 156/630.1, 148/DIG. 59, 219/99, 438/77, 438/82
• US Class Current: 438/694
• CPC Class Codes: C09K 13/08 containing a fluorine compound
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: Y10S 148/059 Germanium on silicon or Ge-Si on III-V
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.

Claims

1. A method for using Si--Ge--C in selective etch applications in conjunction with a silicon substrate, comprising:

growing one or more epitaxial layers sequentially, starting at the silicon substrate, wherein at least one of the epitaxial layers comprises Si--Ge--C, wherein the carbon of the Si--Ge--C layer is about 4.5 atomic percent; and

selectively etching the one or more layers adjacent to the Si--Ge--C layer and/or the Si--Ge--C layer wherein the selective etching includes applying a KOH etchant to the Si--Ge--C layer.

2. The method of claim 1, wherein the Si--Ge--C layer etches slower than the one or more adjacent layers.

3. The method of claim 1, wherein the Si--Ge--C layer etches slower than the silicon substrate.

4. The method of claim 1, wherein the etchant is 10-45 wt % KOH--H₂ O and is maintained at a temperature in the range of 50 to 100°

C.

5. The method of claim 1, wherein the etchant is 21 wt % KOH--H₂ O and is maintained at a temperature in the range of 50 to 100°

C.

6. A method for using Si--Ge--C in selective etch applications in conjunction with a silicon, germanium, or silicon-germanium substrate, comprising:

growing one or more epitaxial layers sequentially, starting at the substrate, at least one of which comprises Si--Ge--C, wherein carbon is present in the Si--Ge--C layer(s) in an amount sufficient for etch selectivity with respect to the substrate and/or adjacent epitaxial layers; and

etching the one or more layers adjacent to the Si--Ge--C layer or the Si--Ge--C layer or the substrate with HNA, wherein the carbon content is greater than 2 percent.

8. The method of claim 6 or 7, wherein the carbon is in the range of 4-5 atomic percent.

9. The method of claim 6 or 7, wherein the carbon is about 4.5 atomic percent.

7. A method of forming a silicon-on-insulator material, the method comprising the steps of:

forming a Si--Ge--C epitaxial layer having a carbon concentration greater than 2 percent, sufficient to function as an etch-stop, wherein the Si--Ge--C resides on a surface of a first semiconductor silicon substrate;

forming a second silicon epitaxial layer on the Si--Ge--C alloy layer;

providing a first oxide layer on a surface of the second epitaxial layer;

providing a second oxide layer on a second semiconductor silicon substrate;

bringing into contact the first and second oxide layers thereby bonding together the first and second semiconductor substrates to thereby form a laminated structure;

removing most of the first silicon substrate;

exposing the laminate to a first etchant which preferentially etches the first silicon substrate until the remainder of the first silicon substrate is removed, but only a part of the Si--Ge--C layer is removed; and

exposing the resultant structure to HNA which preferentially etches the Si--Ge--C layer for a time sufficient only to remove the remainder of the Si--Ge--C layer thereby producing a silicon-on-insulator material.