Method of making floating-gate memory-cell array with digital logic transistors

• US 5,907,171 A
• Filed: 11/25/1997
• Issued: 05/25/1999
• Est. Priority Date: 05/18/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Santin, Giovani, Smayling, Michael C., Marotta, Giulio, Matsuoka, Misako A., Fukawa, Satoru
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US08/978,363
• Time in Patent Office: 546 Days
• Field of Search: 257/315, 257/316
• US Class Current: 257/315
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in ultra-violet erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.

Claims

1. A nonvolatile, floating-gate memory with logic transistors, comprising:

a semiconductor body having doping of a first conductivity-type;

at least first and second opposite-conductivity-type diffusion regions having a first depth in said semiconductor body, said opposite-conductivity-type diffusion regions having doping primarily of a second conductivity-type opposite said first conductivity-type;

at least first and second same-conductivity-type diffusion regions having a second depth in said semiconductor body, said first and second same-conductivity-type diffusion regions having doping primarily of said first conductivity-type, said first same-conductivity-type diffusion region encased by said first opposite conductivity-type diffusion region, said second same-conductivity-type diffusion region separated on said substrate from said first and second opposite-conductivity-type diffusion regions; and

at least one floating-gate memory cell in said first same-conductivity-type diffusion region, at least one high-voltage logic transistor in said second opposite-conductivity-type region, and at least one low-voltage logic transistor in said second same-conductivity-type region.

2. The floating-gate memory with logic transistors of claim 1, wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is primarily of N conductivity-type, said second diffusion region is primarily of P conductivity-type.

3. The floating-gate memory with logic transistors of claim 1, wherein during erasing operation said first opposite-conductivity-type diffusion region and said first same conductivity-type diffusion region are connected to a positive potential with respect to the potential of said semiconductor body.

4. The floating-gate memory with logic transistors of claim 1, wherein Fowler-Nordheim tunnelling is used to erase said floating gate of memory cell.

5. The floating-gate memory with logic transistors of claim 1, wherein said floating-gate memory cell is part of an X-cell memory array having single-dopant sources and drains.

6. The floating-gate memory with logic transistors of claim 1, further including field oxide regions on the surface of said semiconductor substrate, said field oxide regions over the edges of said diffusion regions.

7. The floating-gate memory with logic transistors of claim 1, further including field oxide regions on the surface of said semiconductor substrate, said field oxide regions over the edges of said diffusion regions and within said diffusion regions surrounding at least one connection point.

8. The floating-gate memory with logic transistors of claim 1, further including field oxide regions on the surface of said semiconductor substrate, said field oxide regions surrounding connection points to said diffusion regions, said first opposite-conductivity-type diffusion region and said first same-conductivity-type diffusion regions having multiple connection points at the periphery of said diffusion regions.

9. The floating-gate memory with logic transistors of claim 1, further including diffused contacts in said first same-conductivity-type diffusion region, wherein said diffused contacts include additional doping of said same-conductivity-type.

10. The floating-gate memory with logic transistors of claim 1, further including diffused contacts in said first same conductivity-type diffusion region, wherein said diffused contacts are connected to doped polysilicon.