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Interpolation circuit for encoder

  • US 5,907,298 A
  • Filed: 10/14/1997
  • Issued: 05/25/1999
  • Est. Priority Date: 10/29/1996
  • Status: Expired due to Term
First Claim
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1. An interpolation circuit for an encoder, comprising:

  • a clock generator which generates a first clock and a second clock, the second clock being synchronized with the first clock and having a higher frequency than the first clock;

    a phase angle detecting circuit which samples two-phase sinusoidal signals output from the encoder with 90°

    phase-shift each other by the first clock, and then digital-processes the resultant sampled values to detect phase angle of the two-phase sinusoidal signals so as to sequentially output phase angle data, each phase angle data corresponding to the respective sampling phase defined by the first clock;

    a data updating circuit which sequentially input the phase angle data output from the phase angle detecting circuit, and then updates the current phase angle data by the subsequent phase angle data in such a manner as to calculate a differential between the current phase angle data and the subsequent phase angle data, and then adds the differential data, whose upper limit is predetermined, to the current phase angle data, thereby holding sequentially updated phase angle data;

    an integrating circuit which integrates the differential data by the second clock to hold the integrated value which is to be reset by the first clock;

    a carry detecting circuit which detects that the integrated value is over the ratio of the first clock period to the second clock period to output a carry detecting signal; and

    a two-phase square wave generating circuit which generates two-phase square wave, state of which changes synchronously with the second clock at each timing of the carry detecting signal.

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