Interpolation circuit for encoder

• US 5,907,298 A
• Filed: 10/14/1997
• Issued: 05/25/1999
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Mitutoyo Corporation
• Original Assignee: Mitutoyo Corporation
• Inventors: Kiriyama, Tetsuro, Teraguchi, Mikiya
• Primary Examiner(s): Williams, Howard L.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/949,620
• Time in Patent Office: 588 Days
• Field of Search: 341/111, 341/116, 318/600, 318/661, 318/602
• US Class Current: 341/111
• CPC Class Codes: G01D 5/24404 Interpolation using high frequency signals
• CPC Class Codes: H03M 1/207 using a digital interpolation circuit
• CPC Class Codes: H03M 1/303 Circuits or methods for processing the quadrature signals

Abstract

An interpolation circuit of an encoder of which dynamic accuracy is improved is disclosed. The phase angle data detecting circuit 1 detects to store the phase angle data PH for each of the first clock CK1. The phase angle data PH is input to the updating circuit 2 in which the current data CNT is subtracted from the subsequent phase angle data PH so as to be updated. The differential data DX is limited within an upper limit to be added to the current data CNT. The integrating circuit 3 integrates the differential data DELTA1, whose upper limit is predetermined, by the second clock CK2 to generate the carry signal QUADEN at each timing when the integrated value leads to the period ratio of CK1 to CK2. The two-phase square wave generating circuit 5 generates two-phase square wave signals at each timing of the carry signal QUADEN. The over-speed detecting circuit 6 monitors the differential data DX to generate the over-speed alarm signal OSALM under a predetermined condition.

Claims

1. An interpolation circuit for an encoder, comprising:

a clock generator which generates a first clock and a second clock, the second clock being synchronized with the first clock and having a higher frequency than the first clock;

a phase angle detecting circuit which samples two-phase sinusoidal signals output from the encoder with 90°

phase-shift each other by the first clock, and then digital-processes the resultant sampled values to detect phase angle of the two-phase sinusoidal signals so as to sequentially output phase angle data, each phase angle data corresponding to the respective sampling phase defined by the first clock;

a data updating circuit which sequentially input the phase angle data output from the phase angle detecting circuit, and then updates the current phase angle data by the subsequent phase angle data in such a manner as to calculate a differential between the current phase angle data and the subsequent phase angle data, and then adds the differential data, whose upper limit is predetermined, to the current phase angle data, thereby holding sequentially updated phase angle data;

an integrating circuit which integrates the differential data by the second clock to hold the integrated value which is to be reset by the first clock;

a carry detecting circuit which detects that the integrated value is over the ratio of the first clock period to the second clock period to output a carry detecting signal; and

a two-phase square wave generating circuit which generates two-phase square wave, state of which changes synchronously with the second clock at each timing of the carry detecting signal.

2. The interpolation circuit according to claim 1, wherein the phase angle detecting circuit comprises:

a sample-and-hold circuit which samples the two-phase sinusoidal signals by the first clock and holds the sampled values;

an A/D converter which converts the sampled values to a set of digital data;

a look-up table memory which outputs a phase angle data based on the set of digital data; and

a first data storing circuit which sequentially stores the phase angle data read out from the look-up table memory synchronously with the first clock.

3. The interpolation circuit according to claim 2, wherein the data updating means comprises;

a second storing circuit which sequentially stores the phase angle as a current phase angle data which is to be updated by the subsequent phase angle data from the first storing circuit synchronously with the first clock;

a subtracter which subtracts the current phase angle data in the second storing circuit from the subsequent phase angle data in the first storing circuit to output a differential data;

a limiter which limits the differential data as to have an upper limit that is smaller than the ratio of the first clock period to the second clock period; and

an adder which adds the differential data whose upper limit is predetermined to the current phase angle data in the second storing circuit, thereby updating the current phase angle data.

4. The interpolation circuit according to claim 2, wherein the data updating circuit comprises;

a second storing circuit which sequentially stores the phase angle data as a current phase angle data which is to be updated by the subsequent phase angle data from the first storing circuit synchronously with the first clock;

a subtracter which subtracts the current phase angle data in the second storing circuit from the subsequent phase angle data in the first storing circuit to output a differential data;

a detecting circuit which detects the absolute and the polarity of the differential data;

a limiter which limits the absolute of the differential data as to have an upper limit that is smaller than the ratio of the first clock period to the second clock period;

a polarity adding circuit which adds the polarity data to the differential data whose upper limit is predetermined; and

an adder which adds the differential data on which the polarity data is added to the current phase angle data in the second storing circuit, thereby updating the current phase angle data.

5. The interpolation circuit according to claim 1, further comprising an over-speed detecting circuit which detects over-speed state by monitoring the differential data in the data updating circuit.

6. The interpolation circuit according to claim 5, wherein the over-speed detecting circuit comprises:

a comparator which compares the absolute of the differential data with a reference value to output a over-speed signal for each timing when the absolute of the differential data is higher than the reference value; and

an alarm circuit which input the over-speed signals synchronously with the first clock to output an over-speed alarm signal in such a condition that the over-speed signals are subsequently output over a predetermined number.

7. The interpolation circuit according to claim 5, wherein the over-speed detecting circuit comprises:

a comparator which compares the absolute of the differential data with a reference value to output a over-speed signal for each timing when the absolute of the differential data is higher than the reference value;

a polarity detecting circuit which detects the polarity of the differential data; and

an alarm circuit which input the over-speed signals synchronously with the first clock to output an over-speed alarm signal in such a condition that the over-speed signals are subsequently output, and thereunder the polarity detecting circuit detects the inversion of the polarity of the differential data.

8. An interpolation circuit for an encoder, comprising:

a phase angle detecting circuit which sequentially detects phase angle of two-phase sinusoidal signals output from the encoder with 90°

phase-shift each other by use of digital signal processing for each period of a first clock to sequentially output phase angle data, each phase angle data corresponding to the respective sampling phase defined by the first clock for sampling the two-phase sinusoidal signals;

a calculating circuit which calculates a differential between each of the phase angle data sequentially output from the phase angle detecting circuit and one period preceding phase angle data;

a time-interpolating circuit which synchronously disperses the differential data output from the calculating circuit with a second clock which has a higher frequency than the first clock so as to output uniformly dispersed pulses within the first clock period; and

a two-phase square wave generating circuit which generates digital two-phase square wave signals, state of which changes synchronously with the second clock at each timing of the uniformly dispersed pulses.