Analog-to digital converter with delta-sigma modulator

• US 5,907,299 A
• Filed: 10/23/1996
• Issued: 05/25/1999
• Est. Priority Date: 10/23/1996
• Status: Expired due to Term

• Current Assignee: Sonic Innovations Incorporated (William Demant Fonden)
• Original Assignee: Sonix Technology Company Limited
• Inventors: Green, Robert S., Davis, Keith L.
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/731,963
• Time in Patent Office: 944 Days
• Field of Search: 341/118, 341/120, 341/155, 341/143
• US Class Current: 341/143
• CPC Class Codes: H03M 3/02 Delta modulation, i.e. one-bit differential modulation H03M3/30 takes precedence

Abstract

An analog-to-digital converter according to the present invention comprising a comparator having first and second inputs, and an output, the comparator comparing an analog input voltage at the first input to a tracking voltage at the second input to place a digital output on the comparator output in response thereto, a voltage switching matrix having an input connected to the output of the comparator and an output, an integrator having an input connected to the output of the voltage switching matrix and an output connected to the second input of the comparator to complete a feedback loop and to provide the tracking signal to the second input of the comparator, and a digital filter coupled to the output of the comparator, the digital filter to form a digital output corresponding to the analog input signal at the first input of the comparator.

Claims

1. An analog-to-digital converter comprising:

a comparator having first and second inputs, and an output, said comparator comparing an analog input voltage at said first input to a tracking voltage at said second input to place a digital output on said comparator output in response thereto;

a voltage switching matrix having an input connected to said output of said comparator and an output;

an integrator having an input connected to said output of said voltage switching matrix and an output connected to said second input of said comparator to complete a feedback loop and to provide said tracking signal to said second input of said comparator; and

a digital filter coupled to said output of said comparator, said digital filter to form a digital output corresponding to said analog input signal at said first input of said comparator.

2. The analog-to digital converter of claim 1, wherein said comparator comprises:

a positive comparator having a first input coupled to said analog input voltage, a second input coupled to said tracking voltage, an enable input coupled to a first select signal which enables said positive comparator when said analog input voltage is greater than a preset voltage level, a strobe input coupled to a strobe signal to turn on said positive comparator, and an output;

a negative comparator having a first input coupled to said analog input voltage, a second input coupled to said tracking voltage, an enable input coupled to a second select signal to enable said negative comparator when said analog input voltage is less than a preset input voltage level, a strobe input coupled to said strobe signal to turn on said negative comparator, and an output; and

an output module having a first input connected to said output of said positive comparator and a second input connected to said output of said negative comparator, and first and second outputs to provide said comparator output to said voltage switching matrix and to said digital filter.

3. The analog-to digital converter of claim 2, wherein said output module comprises:

first and second NOR gates having first and second inputs and an output, said first input of said first NOR gate connected to a first output of said positive comparator, said second input of said first NOR gate connected to a first output of said negative comparator, said first input of said second NOR gate connected to a second output of said positive comparator, and said second input of said second NOR gate connected to a second output of said negative comparator,

first and second NAND gates having first and second inputs and an output, said first input of said first NAND gate connected to said output of said first NOR gate, said second input of said first NAND gate connected to said output of said second NAND gate, said first input of said second NAND gate connected to said output of said second NOR gate, and said second input of said first NAND gate connected to said output of said first NAND gate.

4. The analog-to digital converter of claim 1, wherein said digital filter comprises:

an up/down counter having an input coupled to said output of said comparator, an enable input, a reset input, and an output;

an up counter having an enable/count input, and an overflow output coupled to a reset input;

said overflow output coupled to said reset input of said up/down counter; and

a register having a data input connected to said output of said up/down counter, and an enable input connected to said overflow output of said up counter.

5. The analog-to-digital converter of claim 1, further including a preamplifier having an input connected to said analog input voltage, and an output connected to said first comparator input, said preamplifier to provide gain to said analog input voltage to normalize said analog input signal to be in a range of about one-half to all of a rail-to-rail potential of said comparator.

6. An analog-to-digital converter comprising:

a comparator having first and second inputs, and an output, said comparator comparing an analog input voltage at said first input to a tracking voltage at said second input to place a digital output on said comparator output in response thereto;

a first capacitor having a first electrode connected to a first reference voltage and having a second electrode coupled to said first reference voltage in response to a first digital output level from said comparator and coupled to a second reference voltage in response to a second digital output level from said comparator;

a second capacitor having a first electrode connected to said first reference voltage and a second electrode coupled to said second electrode of said first capacitor by at least one switching device and connected to said second input of said comparator, said second capacitor having a capacitance greater than a capacitance of said first capacitor, and said second capacitor storing said tracking voltage for comparison to said analog input voltage by said comparator; and

a digital filter coupled to said output of said amplifier, said digital filter to form a digital output corresponding to said analog input voltage at said first input of said comparator.

7. The analog-to digital converter of claim 6, wherein said comparator comprises:

a positive comparator having a first input coupled to said analog input voltage, a second input coupled to said tracking voltage, an enable input coupled to a first select signal which enables said positive comparator when said analog input signal is greater than a preset voltage level, a strobe input coupled to a strobe signal to turn on said positive comparator, and an output;

a negative comparator having a first input coupled to said analog input voltage, a second input coupled to said tracking voltage, an enable input coupled to a second select signal to enable said negative comparator when said analog input voltage is less than a preset input voltage level, a strobe input coupled to said strobe signal to turn on said negative comparator, and an output; and

an output module having a first input connected to said output of said positive comparator and a second input connected to said output of said negative comparator, and first and second outputs to provide said first and second digital output levels from said comparator and said digital filter.

8. The analog-to digital converter of claim 7, wherein said output module comprises:

first and second NOR gates having first and second inputs and an output, said first input of said first NOR gate connected to a first output of said positive comparator, said second input of said first NOR gate connected to a first output of said negative comparator, said first input of said second NOR gate connected to a second output of said positive comparator, and said second input of said second NOR gate connected to a second output of said negative comparator,

first and second NAND gates having first and second inputs and an output, said first input of said first NAND gate connected to said output of said first NOR gate, said second input of said first NAND gate connected to said output of said second NAND gate, said first input of said second NAND gate connected to said output of said second NOR gate, and said second input of said first NAND gate connected to said output of said first NAND gate.

9. The analog-to digital converter of claim 6, wherein said digital filter comprises:

an up/down counter having an input coupled to said output of said comparator, an enable input, a reset input, and an output;

an up counter having an enable/count input, and an overflow output coupled to a reset input;

said overflow output coupled to said reset input of said up/down counter; and

a register having a data input connected to said output of said up/down counter, and an enable input connected to said overflow output of said up counter.

10. The analog-to-digital converter of claim 6, further including a preamplifier having an input connected to said analog input voltage, and an output connected to said first comparator input, said preamplifier providing gain to said analog input signal to normalize said analog input voltage to be in a range of about one-half to all of a rail-to-rail potential of said comparator.

11. The analog-to digital converter of claim 6, wherein said capacitance of said second capacitor has a ratio to said capacitance of said first capacitor in a range of about two-to-one to about one hundred and twenty-eight-to-one.

12. The analog-to digital converter of claim 6, wherein said capacitance of said second capacitor has a ratio to said capacitance of said first capacitor of about sixty-four-to-one.

13. A method for performing an analog-to-digital conversion comprising the steps of:

1) comparing an analog input voltage to a tracking voltage to generate a digital up voltage when said analog input voltage is greater than said tracking voltage or a digital down voltage when said analog input voltage is less than said tracking voltage;

2) incrementing an accumulator in response to said digital up voltage or decrementing said accumulator in response to said digital down voltage;

3) incrementing said tracking voltage in response to said digital up voltage or decrementing said tracking voltage in response to said digital down voltage;

4) repeating steps 1 through 3 a predetermined number of times; and

next

5) outputting a digital value from said accumulator, said digital value in said accumulator being related to the digital conversion value of an average of said analog input signals.

14. The method for performing an analog-to-digital conversion of claim 13, wherein step 3 comprises the substeps of:

charging a first capacitor to Vdd in response to said digital up voltage or discharging said first capacitor to ground in response to said digital down voltage,

sharing charge on said first capacitor with charge forming said tracking voltage on a second capacitor to increment or decrement said tracking voltage, said second capacitor having a capacitance greater than a capacitance of said first capacitor.

15. The method for performing an analog-to-digital conversion of claim 14, wherein said capacitance of said second capacitor has a ratio to said capacitance of said first capacitor in a range of about two-to-one to about one hundred and twenty-eight-to-one.

16. The method for performing an analog-to-digital conversion of claim 14, wherein said capacitance of said second capacitor has a ratio to said capacitance of said first capacitor of about sixty-four-to-one.

17. A method for performing an analog-to-digital conversion comprising the steps of:

1) comparing an analog input voltage to a predetermined voltage;

2) enabling a first comparator when said analog input voltage is greater than said predetermined voltage to compare said analog input voltage to a tracking voltage and generate a digital up voltage when said analog input voltage is greater than said tracking voltage or a digital down voltage when said analog input voltage is less than said tracking voltage;

3) enabling a second comparator when said analog input voltage is less than said predetermined voltage to compare said analog input voltage to a tracking voltage and generate said digital up voltage when said analog input voltage is greater than said tracking voltage or said digital down voltage when said analog input voltage is less than said tracking voltage;

4) incrementing an accumulator in response to said digital up voltage or decrementing said accumulator in response to said digital down voltage;

5) incrementing said tracking voltage in response to said digital up voltage or decrementing said tracking voltage in response to said digital down voltage;

6) repeating steps 1 through 5 a predetermined number of times; and

next

7) outputting a digital value from said accumulator, said digital value in said accumulator being related to the digital conversion value of an average of said analog input signals.

18. The method for performing an analog-to-digital conversion of claim 17, wherein step 5 comprises the substeps of:

charging a first capacitor to Vdd in response to said digital up voltage or discharging said first capacitor to ground in response to said digital down voltage,

sharing charge on said first capacitor with charge forming said tracking voltage on a second capacitor to increment or decrement said tracking voltage, said second capacitor having a capacitance greater than a capacitance of said first capacitor.

19. The method for performing an analog-to-digital conversion of claim 18, wherein said capacitance of said second capacitor has a ratio to said capacitance of said first capacitor in a range of about two-to-one to about one hundred and twenty-eight-to-one.

20. The method for performing an analog-to-digital conversion of claim 18, wherein said capacitance of said second capacitor has a ratio to said capacitance of said first capacitor of about sixty-four-to-one.