Electrically selectable redundant components for an embedded DRAM

• US 5,907,511 A
• Filed: 12/23/1997
• Issued: 05/25/1999
• Est. Priority Date: 12/23/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Crafts, Harold S.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US08/997,503
• Time in Patent Office: 518 Days
• Field of Search: 365/210, 365/201, 365/230.03, 365/230.01, 365/200, 365/191, 365/230.06, 365/186
• US Class Current: 365/191
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A DRAM array embedded in an IC, ASIC or a SLIC includes a plurality of redundant functional elements and a substitution circuit which responds to signals communicated from a bus to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array. The redundant elements include bit blocks and word line groups. The substitution circuit includes a controllable selector which electrically connects selected ones of the bit blocks and word lines to respond to data and address signals communicated on the bus. A register responds to bus control signals and supplies signals to achieve connection of the redundant elements. The defective elements are identified, and the replacement redundant elements are substituted, by testing the elements of the DRAM array for proper functionality and processing the results of the test.

Claims

1. An embedded DRAM array which includes a bus connected to the DRAM array by which multiple signals are communicated with the DRAM array, said DRAM array comprising:

a plurality of redundant functional elements; and

a substitution circuit responsive to a plurality of control signals communicated over the bus, the substitution circuit responding to each different control signal to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array and to electrically disconnect the defective elements and any not-selected redundant elements from operation within the DRAM array, the ones of the elements which are connected and disconnected determined by the control signals, the substitution circuit changing the connected and disconnected ones of the functional elements in response to each different subsequent control signal and without regard to the connection and disconnection of any previously connected and disconnected elements resulting from a previous control signal.

2. DRAM array as defined in claim 1 wherein said substitution circuit further comprises:

a register responsive to each control signal communicated over the bus to supply a substitution control signal indicative of each selected redundant element to be connected as a replacement for a defective element; and

a controllable selector connected to each redundant element and responsive to the substitution control signal to connect each selected element for communication with the bus and to disconnect each defective and not-selected element from communication with the bus.

3. A DRAM array as defined in claim 2 wherein:

the controllable selector is connected to at least two redundant elements; and

the controllable selector connects one of the redundant elements for communication with the bus and disconnects the other redundant element from communication with the bus in response to the substitution control signal.

4. A DRAM array as defined in claim 2 wherein:

the controllable selector is connected to at least three redundant elements; and

the controllable selector connects one of the three redundant elements for communication with the bus and disconnects the other two redundant element from communication with the bus in response to the substitution control signal.

5. A DRAM array as defined in claim 2 wherein:

each controllable selector includes a register, the registers of all of the controllable selectors being connected in series, and the substitution control signal is a serial signal shifted serially into the serially-connected registers of the controllable selectors.

6. A DRAM array as defined in claim 2 wherein:

the redundant elements comprise a plurality of bit blocks, the predetermined number of bit blocks being at least one greater than a predetermined number of bit blocks required for a fully functional DRAM array, each bit block comprising a plurality of bit lines; and

the controllable selector comprises a bit block selector which connects selected ones of the bit blocks to the bus to read and write data signals to and from the bus.

7. A DRAM array as defined in claim 6 further comprising:

a bit line decoder associated with each bit block, the bit line decoder connected to the bus to respond to bit line address signals; and

wherein;

the bit block selector connects the bit line decoder of the selected bit block to the bus.

8. A DRAM array as defined in claim 7 wherein:

each bit block comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix-like configuration with each cell connected to a bit line and a word line; and

the controllable selector also comprises a word line selector which connects selected ones of the word lines of each bit block to function in response to bus word line address signals.

9. A DRAM array as defined in claim 8 wherein:

the corresponding word lines of all of the bit blocks are connected together; and

further comprising;

a word line decoder connected to the bus to receive the bus word line address signals and to deliver a word line select signal in response to a predetermined word line address signal; and

wherein;

the word line selector is connected to the word line decoder to receive the word line select signal and apply the word line select signal simultaneously to all of the selected and connected word lines of the bit blocks.

10. A DRAM array as defined in claim 9 further comprising:

a group word line selector connected to a predetermined group of word lines and to the word line selector, the group word line selector is further connected to the bus to receive word line address signals indicative of the ones of the group of word lines to which the group word line selector is connected; and

wherein;

the word line selector applies the word line select signal to the group word line selector; and

the group word line selector applies the word line select signal to the selected one of the word lines of the group of word lines corresponding to the word line address signals applied to the group word line selector.

11. A DRAM array as defined in claim 2 wherein:

the redundant elements comprise word lines; and

the controllable selector comprises a word line selector which connects selected ones of the word lines to function in response to bus address signals.

12. A DRAM array as defined in claim 11 further comprising:

a word line decoder connected to the bus to receive bus address signals and to deliver a word line select signal in response to a predetermined bus address signal; and

wherein;

the word line selector is connected to the word line decoder to receive the word line select signal and apply the word line select signal to the selected word line.

13. An embedded DRAM array which includes a bus connected to the DRAM array by which signals are communicated with the DRAM array, said DRAM array comprising:

a Plurality of redundant functional elements, the elements comprise word lines;

a substitution circuit responsive to signals communicated over the bus to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array and to electrically disconnect the defective elements and any not-selected redundant elements from operation within the DRAM array; and

wherein;

the redundant elements comprise word lines;

the substitution circuit comprises a word line selector which connects selected ones of the word lines to function in response to bus address signals;

a word line decoder connected to the bus to receive bus address signals and to deliver a word line select signal in response to a predetermined bus address signal;

the word line selector connected to the word line decoder to receive the word line select signal and apply the word line select signal to the selected word line; and

further comprising;

a group word line selector connected to a predetermined group of word lines and to the word line selector, the group word line selector is further connected to the bus to receive word line address signals indicative of the ones of the group of word lines to which the group word line selector is connected; and

wherein;

the word line selector applies the word line select signal to the group word line selector; and

the group word line selector applies the word line select signal to the selected one of the word lines of the group of word lines corresponding to the word line address signals applied to the group word line selector.

14. A DRAM array as defined in claim 13 wherein:

the group word line selector is connected to a group of four word lines and applies the word line select signal to a selected one of the four connected word lines.

15. A DRAM array as defined in claim 13 wherein:

the DRAM array comprises a plurality of bit blocks;

each bit block comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix-like configuration with each cell connected to a bit line and a word line;

the corresponding word lines of all of the bit blocks are connected together;

the group word line selector applies the word line select signal simultaneously to the selected ones of the corresponding word lines of all of the bit blocks.

16. An embedded DRAM array which includes a bus connected to the DRAM array by which signals are communicated with the DRAM array, said DRAM array comprising:

a plurality of redundant functional elements;

a substitution circuit responsive to signals communicated from the bus to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array and to electrically disconnect the defective elements and any not-selected redundant elements from operation within the DRAM array; and

wherein;

the DRAM array is part of an IC which also includes a processor connected to the bus; and

the processor executes a program which supplies signals to the bus for testing the redundant components of the DRAM array, determines functional and defective components based on the results of the test, and supplies the signals on the bus to the substitution circuit based on the determination of the functional and defective components.

17. A DRAM array as defined in claim 16 wherein:

the processor executes the program to determine the functional and defective components each time that power is initially supplied to the DRAM array.

18. A DRAM array as defined in claim 16 wherein the IC is a SLIC.

19. A DRAM array embedded in a SLIC, comprising:

a bus having a plurality of conductors over which address, control and data signals are supplied to the DRAM array from other components of the SLIC;

a predetermined plurality of bit blocks, each bit block having a plurality of bit lines and a plurality of word lines, the numbers of bit lines and word lines being greater than the number of bit lines and word lines required for a functional DRAM array; and

a selector circuit connected to the bus and the bit blocks and responsive to control signals supplied on the bus to connect selected ones less than all of the word lines or the bit lines to the bus for response to address signals from the bus and to prevent the ones of the word or bit lines other than the selected ones from responding to address signals.

20. A DRAM array as defined in claim 19 wherein:

the number of bit blocks of the predetermined plurality is at least one greater than a predetermined number of bit blocks required for a fully functional DRAM array; and

the selector circuit comprises a bit block selector which connects selected ones of the bit blocks to the bus to communicate data signals with the bus in response to bit line address signals and to prevent other ones of bit blocks from communicating data signals with the bus in response to bit line address signals.

21. A DRAM array as defined in claim 19 wherein:

each bit block includes a predetermined plurality of word line groups, the number of word line groups of the predetermined plurality of word lines is at least one greater than the number of word line groups required for a fully functional DRAM array, each group having at least one word line; and

the selector circuit comprises a word line selector which connects selected ones of the word line groups to the bus to respond to word line address signals supplied on the bus and to disconnect other ones of word line groups from the bus and prevent the other ones of the word lines from responding to word line address signals on the bus.

22. A DRAM array as defined in claim 21 further comprising:

a word line decoder for responding to the word line address signals on the bus; and

a group word line selector connected to a plurality of word lines connected to the bit blocks and constituting a group of word lines, the group word line selector responding to word line address signals from the bus; and

wherein

the word line selector is connected between the word line decoder and the group word line selector.

23. A method of substituting selected ones of a plurality of redundant functional elements for defective elements in a DRAM array embedded in an IC which includes a bus connected to the DRAM array by which signals are communicated with the DRAM array, said method comprising the steps of:

electrically switching selected ones of the plurality redundant elements into operation in the DRAM array as fully functional replacements for corresponding defective elements of the DRAM array;

electrically switching the defective elements and any not-selected redundant elements out of operation in the DRAM array; and

sending substitution signals on the bus to control the electrical switching.

24. A method as defined in claim 23 further comprising the steps of:

storing the substitution signals in registers; and

maintaining the selected ones of the redundant elements in operation and maintaining the defective and not-selected redundant elements out of operation in response to the substitution signal stored in the registers.

25. A method as defined in claim 23 wherein the redundant elements comprise a plurality of bit blocks, the predetermined number of bit blocks being at least one greater than a predetermined number of bit blocks required for a fully functional DRAM array, each bit block comprising a plurality of bit lines;

and said method further comprises the steps of;

electrically switching selected ones of the bit blocks to the bus to read and write data signals to and from the bus over the bit lines.

26. A method as defined in claim 23 wherein the redundant elements comprise a plurality of word line groups, and said method further comprises the steps of:

electrically switching selected ones of the word line groups of each bit block to function in response to bus word line address signals.

27. A method as defined in claim 26 further comprising the steps of:

electrically switching a predetermined group of word line groups to function in response to bus word line address signals.

28. A method as defined in claim 23 further comprising the steps of:

executing a test program for testing the redundant components of the DRAM array;

determining the functional and defective components based on the results of the test program; and

determining which of the redundant elements to electrically switch into and out of operation based on the results of the test program.

29. A method as defined in claim 28 further comprising the step of:

executing the test program each time that power is initially supplied to the DRAM array.

30. A method as defined in claim 28 wherein the IC is a SLIC.