Memory circuit yield generator and timing adjustor

• US 5,907,517 A
• Filed: 11/12/1997
• Issued: 05/25/1999
• Est. Priority Date: 06/14/1990
• Status: Expired due to Term

• Current Assignee: Creative Integrated Systems Incorporated
• Original Assignee: Creative Integrated Systems Incorporated
• Inventors: Komarek, James A., Padgett, Clarence W.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/967,878
• Time in Patent Office: 559 Days
• Field of Search: 365/210, 365/205, 365/203, 365/104, 365/189.07, 365/225.7
• US Class Current: 365/189.07
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/126 Virtual ground arrays
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.

Claims

1. An improvement in a semiconductor memory having a dummy bit line, DMY1, having memory cells, having a sense time when said memory cells will be read, and simulating the worst case within said memory for reading a logical one, comprising:

means for providing a plurality of selectable capacitors; and

programmable means for selectively coupling said capacitors to said dummy bit line DMY1 so that sense time within said semiconductor memory is programmably varied, said dummy bit line, DMY1, being coupled to said semiconductor memory to determine said sense time when memory cells within said semiconductor memory will be read,

wherein said programmable means comprises a plurality of links, said links having a programmably determined conductivity, one of said programmable links being coupled to each one of said capacitors to selectively couple said corresponding capacitor to said dummy bit line, DMY1.

2. An improvement in a semiconductor memory of the type having a dummy bit lines simulating worst cases for reading a logical one and for reading a logical zero, the improvement comprising:

means for adjusting a rate of voltage change in a logical one dummy bit line;

means for dampening noise in a logical zero dummy bit line; and

means for controlling a read time cycle of the semiconductor memory in response to a comparison between the logical one dummy bit line and the logical zero dummy bit line.

3. The improvement of claim 2, wherein the means for adjusting comprises:

means for providing a plurality of selectable capacitors; and

programmable means for selectively coupling said capacitors to said logical one dummy bit line.

4. The improvement of claim 2, wherein the means for dampening comprises:

means for providing a plurality of selectable capacitors; and

programmable means for selectively coupling said capacitors to said logical zero dummy bit line.