Distributed processing method for checking status of processor in electronic switching system

• US 5,907,670 A
• Filed: 07/24/1996
• Issued: 05/25/1999
• Est. Priority Date: 07/24/1995
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kwang-Bae
• Primary Examiner(s): Hua, Ly
• Application Number:
  US08/685,585
• Time in Patent Office: 1,035 Days
• Field of Search: 395/182.02, 395/182.08, 395/182.09, 395/183.09, 395/185.09
• US Class Current: 714/4.1
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: H04L 41/0604 using filtering, e.g. reduction of information by using priority, element types, position or time
• CPC Class Codes: H04L 43/0817 by checking functioning

Abstract

An electronic switching system having a plurality of processors connected to an internal switching network in a chain structure of a linked list form and a maintenance processor for checking status of each individual processor connected to the internal switching network. The status of the processors is checked through a mutual status checking process between unit processors, and if any processor contains any abnormality, such abnormal status of the processor is notified to the maintenance processor.

Claims

1. A distributed processing method for checking a status of each unit processor in an electronic switching system having a maintenance processor for controlling operation of a plurality of unit processors within said electronic switching system, said method comprising the steps of:

interconnecting all unit processors in a dual link chain structure for mutual communications with adjacently situated and interconnected unit processors;

checking a status of a designated one of said unit processors interconnected in said dual link chain structure by a mutual status check from said adjacently situated and interconnected unit processors; and

notifying an abnormal status of said designated unit processor to said maintenance processor, when said designated unit processor exhibits an abnormal status.

2. A distributed processing method for checking a status of a unit processor in an electronic switching system having a maintenance processor for controlling operations of a plurality of unit processors within said electronic switching system, said method comprising the steps of:

indexing identification values of all the unit processors and then forming a processor path table in a structure where a path of each processor is matched corresponding to each of the indexed identification values of said unit processors;

periodically performing a mutual status check between unit processors adjacent to each other by using said processor path table; and

controlling said processor path table according to the status check of said unit processor.

3. The method of claim 2, further comprised of said processor path table comprising indexes in accordance with identifications of all the processors and inherent path values which are matched corresponding to said indexes and indicate the present status of the processor path and the path of adjacent processors.

4. The method of claim 3, further comprised of each of said inherent path values being provided as a specific value in a situation when said unit processor is packaged to operate abnormally, and being provided as a dummy value in a situation when said unit processor is unpackaged or is operating abnormally.

5. The electronic switching system of claim 3, further comprised of each of said inherent path values being provided as a specific value in a situation when a corresponding unit processor is packaged to operate abnormally, and being provided as a dummy value in a situation when said corresponding unit processor is unpackaged or is operating abnormally.

6. A distributed processing method for checking a status of a unit processor in an electronic switching system having a maintenance processor for controlling a plurality of unit processors within said electronic switching system, said method comprising the steps of:

indexing identification values of all the unit processors and then forming a processor path table in a structure where a path of each unit processor is matched corresponding to each of the indexed identification values of said unit processors;

searching an adjacent processor in said processor path table to send a message requesting a check sum value of the processor path table of said adjacent processor and waiting for a response, upon a time-out period of a periodic timer for the status check of each unit processor;

comparing a received check sum value with a value of the corresponding unit processor, when a response is received from said adjacent processor within a designated waiting time period;

requesting a copy of a master processor path table to said maintenance processor, when said received check sum value does not correspond to the value of the corresponding unit processor, and continuing the mutual check by a message, when said adjacent processor is in a normal status;

judging said adjacent processor to be in an abnormal status, when the response is not received within said designated waiting time period, and then notifying the abnormal status of said adjacent processor to said maintenance processor;

performing a test for checking the status of said adjacent processor, by said maintenance processor; and

changing said master processor path table and copying the changed master processor path table to all processors, when the abnormal status is checked through said test for checking the status of the processor.

7. The method of claim 6, further comprised of said maintenance processor receiving a request of the abnormal processor having lower logical processor identification, if two abnormal processors are simultaneously detected to be notified and then abnormalities thereof are identical to each other.

8. The method of claim 7, further comprised of said maintenance processor processing the received requests at a given time interval, when faults are coincidentally generated by said plurality of unit processors and a plurality of change requests from said plurality of unit processors are simultaneously received by said maintenance processor.

9. The method of claim 6, further comprised of said processor path table comprising indexes in accordance with identifications of all the processors and inherent path values which are matched corresponding to said indexes and indicate the present status of the processor path and the path of adjacent processors.

10. The method of claim 9, further comprised of each of said inherent path values being provided as a specific value in a situation when said unit processor is packaged to operate abnormally, and being provided as a dummy value in a situation when said unit processor is unpackaged or is operating abnormally.

11. An electronic switching system, comprising:

a maintenance processor; and

a plurality of unit processors interconnected in a dual link chain structure for mutual communications with corresponding indexed identification values formed in a processor path table, each unit processor being mutually checked periodically for abnormality by adjacent unit processors by using said processor path table, and reported such abnormality to said maintenance processor for exclusion from said processor path table.

12. The electronic switching system of claim 11, further comprised of said processor path table comprising indexes in accordance with identifications of all unit processors and inherent path values which are matched corresponding to said indexes and indicate the present status of the processors.