Independent channel coupled to be shared by multiple physical processing nodes with each node characterized as having its own memory, CPU and operating system image

• US 5,907,684 A
• Filed: 05/23/1996
• Issued: 05/25/1999
• Est. Priority Date: 06/17/1994
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sachs, Martin William, Halma, Marten Jan
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Ton, David
• Application Number:
  US08/652,177
• Time in Patent Office: 1,097 Days
• Field of Search: 711/202, 711/201, 395/856, 395/848, 395/881, 395/200.43, 395/674, 395/200.67, 395/892
• US Class Current: 709/237
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function

Abstract

A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is characterized as having its own memory, by either at least one channel which is independent of and coupled to the multiple physical processing nodes or by at least one input/output (I/O) processor, again which is independent of and coupled to the multiple physical processing nodes. The at least one channel and/or the at least one I/O processor couple the multiple physical processing nodes to at least one shared input/output device. Sharing of the at least one channel and/or at least one I/O processor is practical by providing "indirect logical addressing" using logical address tables within the channel subsystem. The logical address tables associate an image identifier (Image_-- ID) and processing node identifier (PN_-- ID) concatenation with an indexed logical address for use in communicating I/O operation parameters across the at least one channel.

Claims

1. A computer system comprising:

multiple physical processing nodes coupled together, each physical processing node having its own memory, at least one CPU and its own at least one operating system image; and

at least one channel independent of and coupled to be shared by said multiple physical processing nodes, said at least one channel coupling said multiple physical processing nodes to at least one I/O device; and

means for sharing the at least one channel between the multiple physical processing nodes such that a first I/O operation initiated at a first Physical processing node of the multiple physical processing nodes and a second I/O operation initiated at a second Physical processing node of the multiple physical processing nodes can each take place over said at least one channel; and

wherein the at least one channel comprises multiple channels, said multiple channels comprising a channel subsystem which is coupled to and shared by said multiple physical processing nodes; and

wherein said means for sharing includes means for providing the channel subsystem with an image identifier (Image_-- ID) and a processing node identifier (PN_-- ID) with initiation of the first I/O operation by the first physical processing node of the multiple physical processing nodes coupled to the channel subsystem.

2. The computer system of claim 1, wherein said channel subsystem includes at least one logical address table for conversion of the Image_-- ID and PN_-- ID from said physical processing node to an associated "indexed logical address" for use in communicating the I/O operation across a channel of said multiple channels comprising the channel subsystem.

3. The computer system of claim 2, wherein the indexed logical address comprises less bits than a number of bits required for the associated Image_-- ID and PN_-- ID.

4. The computer system of claim 2, wherein each physical processing node of the plurality of physical processing nodes has at least one I/O processor, and wherein each I/O processor communicates with at least one I/O device across the channel subsystem.

5. The computer system of claim 3, wherein said at least one logical address table includes a conversion table for converting the Image_-- ID and a PN_-- ID received from the physical processing node of said multiple physical processing nodes originating the I/O operation to the indexed logical address for transmission over the channel of said multiple channels, and a reconversion table for reconverting the indexed logical address to the associated Image_-- ID and PN_-- ID for return of I/O operation status to the physical processing node originating the I/O operation.

6. The computer system of claim 1, further comprising a switch coupling the multiple physical processing nodes to the at least one channel.

7. The computer system of claim 6, wherein each physical processing node of said multiple physical processing nodes comprises a central electronic complex (CEC) and wherein said CECs and said switch comprises a CECPLEX.

8. The computer system of claim 6, further comprising at least one shared I/O processor and means for sharing said at least one shared I/O processor between said multiple physical processing nodes, said at least one shared I/O processor being coupled between said switch and said at least one channel, said means for sharing comprising means for providing to the at least one shared I/O processor an image identifier (Image_-- ID) and a processing node identifier (PN_-- ID) with initiation of the first I/O operation at the first physical processing node of said multiple physical processing nodes.

9. The computer system of claim 8, wherein said at least one I/O device coupled to said at least one channel comprises a plurality of I/O devices coupled to said at least one channel, and wherein said at least one shared I/O processor comprises multiple shared I/O processors, at least some I/O processors of said multiple shared I/O processors being coupled to communicate across said at least one channel with at least one common I/O device of said plurality of I/O devices coupled to said at least one channel.

10. The computer system of claim 9, further comprising means for allowing only said at least some I/O processors of said multiple shared I/O processors to respond to the I/O operation initiation at the physical processing node of said multiple physical processing nodes when said I/O operation requires said at least one common I/O device of the plurality of I/O devices coupled to the at least one channel.

11. The computer system of claim 1, wherein each physical processing node of said multiple physical processing nodes comprises a central electronic complex (CEC).

12. The computer system of claim 1, wherein at least one physical processing node of said multiple physical processing nodes comprises a multiprocessor having multiple CPUs.

13. A computer system comprising:

multiple physical processing nodes coupled together, each physical processing node characterized as having its own memory, at least one CPU and its own at least one operating system image and lacking its own I/O processor; and

at least one input/output (I/O) processor independent of and coupled to be shared by said multiple physical processing nodes, said at least one I/O processor coupling said multiple physical processing nodes to at least one I/O device; and

having

means for sharing the at least one I/O processor between the multiple physical processing nodes such that a first I/O operation initiated at a first physical processing node of the multiple physical processing nodes and a second I/O operation initiated at a second physical processing node of the multiple physical processing nodes can each be processed through said at least one I/O processor; and

wherein said at least one shared I/O processor comprises part of a shared I/O subsystem, said shared I/O subsystem further including a shared channel subsystem coupled between said at least one I/O processor and said at least one I/O device; and

wherein said means for sharing further comprises means for sharing said shared channel subsystem, said means for sharing including means for providing the shared channel subsystem with an image identifier (Image_-- ID) and a processing node identifier (PN_-- ID) with initiation of an I/O operation at a physical processing node of said multiple physical processing nodes, and wherein said shared channel subsystem includes means for converting the Image_-- ID and PN_-- ID to an "indexed logical address" employing at least one logical address table, said indexed logical address being employed to communicate the I/O operation across a channel of said shared channel subsystem.

14. The computer system of claim 13, wherein the indexed logical address comprises less bits than a number of bits required for the Image_-- ID and PN_-- ID, said number of bits required for the Image_-- ID and PN_-- ID being incapable of direct transfer across said channel of said shared channel subsystem.

15. The computer system of claim 14, wherein said at least one logical address table comprises a conversion logical address table and a reconversion logical address table, said conversion logical address table being employed by said means for converting the Image_-- ID and PN_-- ID to the indexed logical address, and wherein said shared channel subsystem further comprises means for reconverting the indexed logical address to the associated Image_-- ID and PN_-- ID, said means for reconverting employing said reconversion logical address table to reconvert the indexed logical address to the Image_-- ID and PN_-- ID for communication back to the physical processing node originating the I/O operation.

16. The computer system of claim 13, wherein each physical processing node of said multiple physical processing nodes comprises a central electronic complex (CEC) and wherein said CECs and said switch comprise a CECPLEX.

17. The computer system of claim 13, further comprising at least one channel coupled between said at least one shared I/O processor and said at least one I/O device, said at least one channel being shared by said multiple physical processing nodes coupled to said at least one shared I/O processor.

18. The computer system of claim 13, wherein each physical processing node of said multiple physical processing nodes comprises a central electronic complex (CEC).

19. The computer system of claim 13, wherein at least one physical processing node of said multiple physical processing nodes comprises a multiprocessor having multiple CPUs.

20. A method for processing input/output (I/O) operations within a computer system comprising a plurality of physical processing nodes coupled together and communicating with at least one I/O device via at least one shared channel, each physical processing node being characterized as having its own memory, at least one CPU and its own at least one operating system image and lacking its own channel subsystem, said at least one shared channel being independent of said plurality of physical processing nodes, said method comprising:

initiating a first I/O operation at a first processing node of said plurality of physical processing nodes, and initiating a second I/O operation at a second processing node of said plurality of physical processing nodes; and

communicating the first I/O operation over the at least one shared channel and communicating the second I/O operation over the at least one shared channel, wherein said first I/O operation and said second I/O operation are each performed employing said at least one shared channel; and

wherein initiating of the first I/O operation comprises providing an image identifier (Image_-- ID) and a processing node identifier (PN_-- ID) to a shared channel subsystem containing the at least one shared channel, and wherein said communicating comprises converting the Image_-- ID and PN_-- ID to an indexed logical address containing less bits than said Image_-- ID and PN_-- ID and using said indexed logical address to communicate the first I/O operation over said at least one shared channel.

21. The method of claim 20, wherein each said converting comprises employing a logical address table within the shared channel subsystem to obtain the indexed logical address.

22. The method of claim 21, further comprising, for each I/O operation, communicating I/O operation status from said at least one shared channel back to the physical processing node originating the I/O operation, said I/O operation status communicating including reconverting the indexed logical address back to the Image_-- ID and PN_-- ID for transmission of said I/O operation status to said physical processing node originating the I/O operation.

23. The method of claim 20, wherein said computer system further comprises at least one shared I/O processor coupled between said plurality of physical processing nodes and said at least one shared channel, and wherein said method comprises employing said at least one shared I/O processor to process said first I/O operation and said second I/O operation.

24. The method of claim 20, wherein each physical processing node of said multiple physical processing nodes comprises a central electronic complex (CEC).

25. A method for processing input/output (I/O) operations within a computer system comprising a plurality of physical processing nodes coupled together and communicating with at least one I/O device via at least one shared I/O processor, each physical processing node characterized as having its own memory, at least one CPU and its own at least one operating system image and lacking its own I/O processor, said at least one shared I/O processor being independent of said plurality of physical processing nodes, said method comprising:

initiating a first I/O operation at a first processing node of said plurality of physical processing nodes, and initiating a second I/O operation at a second processing node of said plurality of physical processing nodes; and

processing the first I/O operation employing said at least one shared I/O processor and processing the second I/O operation employing said at least one shared I/O processor, wherein said first I/O operation and said second I/O operation are each processed by said at least one shared I/O processor; and

wherein said computer system includes a shared channel subsystem coupled between said at least one shared I/O processor and said at least one I/O device, and wherein said method further comprises accomplishing the first I/O operation employing the shared channel subsystem and accomplishing the second I/O operation employing the shared channel subsystem; and

wherein said initiating of the first I/O operation and said initiating of the second I/O operation each comprises providing an image identifier (Image_-- ID) and a processing node identifier (PN_-- ID) to the at least one shared I/O processor, and wherein said accomplishing each comprises converting the Image_-- ID and PN_-- ID to an "indexed logical address" using a logical address table in the shared channel subsystem and employing said indexed logical address to communicate the I/O operation across a channel of the shared channel subsystem coupled to the at least one I/O device, said indexed logical address having less bits than a concatenation of said Image_-- ID and said PN_-- ID.

26. The method of claim 25, wherein said computer system includes a switch, said switch being coupled between said plurality of physical processing nodes and said at least one shared I/O processor, and wherein said method further comprises communicating said first I/O operation and said second I/O operation to said at least one shared I/O processor across said switch.

27. The method of claim 26, wherein said first processing node contains at least one work queue and said second processing node contains at least one work queue, and wherein said communicating of said first I/O operation and said communicating of said second I/O operation across said switch to said at least one shared I/O processor comprise access the at least one work queue of the first processing node to transfer parameters of the first I/O operation to the at least one shared I/O processor and accessing the at least one work queue of the second processing node to transfer parameters of the second I/O operation to the at least one shared I/O processor.

28. The method of claim 27, wherein said computer system further comprises a shared channel subsystem coupling the at least one shared I/0 processor to the at least one I/O device, and wherein said method further comprises employing said at least one shared I/O processor to transfer commands associated with said first I/O operation from said at least one work queue of said first processing node to said shared channel subsystem and to transfer commands associated with said second I/O operation from said at least one work queue of said second processing node to said shared channel subsystem.

29. The method of claim 25, wherein each physical processing node of said multiple physical processing nodes comprises a central electronic complex (CEC).