Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance

• US 5,907,776 A
• Filed: 07/11/1997
• Issued: 05/25/1999
• Est. Priority Date: 07/11/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/891,546
• Time in Patent Office: 683 Days
• Field of Search: 438/268, 438/269, 438/270, 438/271, 438/272, 438/589, 438/273, 438/274, 148/DIG. 126
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.

Claims

1. A method of forming a semiconductor structure comprising the steps of:

(a) providing a substrate having a major surface;

(b) forming at least one trench in said substrate;

(c) forming a body region of a first conductivity type in said substrate, said body region having a diffusion boundary in said substrate;

(d) forming a source region of a second conductivity type in said body region; and

(e) compensating a portion of said body region by implanting material of said second conductivity type in said body region, said portion being proximal to said source region and spaced from said diffusion boundary of said body region and said major so as to reduce the impurity concentration of said first conductivity type in said portion of said body region.

2. The method of forming a semiconductor structure as set forth in claim 1 further including filling said at least one trench with N-type material.

3. The method of forming a semiconductor structure set forth in claim 1 wherein step (a) includes providing a base substrate of said second conductivity type and forming an epitaxial layer of said second conductivity type above said base substrate.

4. The method of forming a semiconductor structure as set forth in claim 1 wherein step (c) includes the substeps of ion implanting material of said body region in said substrate and thereafter diffusing said material of said body region in said substrate.

5. The method of forming a semiconductor structure as set forth in claim 1 wherein step (d) includes the substeps of ion implanting material of said source region in said substrate and thereafter diffusing said material of said source region in said body region.

6. The method of forming a semiconductor structure as set forth in claim 5 wherein step (e) includes ion implanting material of said second conductivity type in said body region at a predetermined distance from said source region.

7. The method of forming a semiconductor structure as set forth in claim 5 wherein step (e) includes successive substeps of ion implanting material of said second conductivity type in said body region at predetermined distances from said source region.

8. The method of forming a semiconductor structure as set forth in claim 1 wherein step (e) is performed prior to step (d).

9. The method of forming a semiconductor structure as set forth in claim 1 further comprising the step of simultaneously diffusing said source region and said compensated portion of said body region after step (e).

10. The method of forming a semiconductor structure as set forth in claim 1 further comprising forming a gate region formed of material of N-type conductivity dielectrically separated from said body region.

11. The method of forming a semiconductor structure as set forth in claim 1 wherein said first conductivity type is of N-type and said second conductivity is of P-type.

12. The method of forming a semiconductor structure as set forth in claim 1 wherein the implanting material in step (e) is boron.

13. A method of forming a semiconductor structure having a trench gate with a gate threshold voltage, said method comprising the steps of:

(a) providing a substrate having a major surface;

(b) forming a body region of a first conductivity type in said substrate, said body region having a diffusion boundary in said substrate;

(c) forming a source region of a second conductivity type in said body region; and

(d) compensating a portion of said body region by implanting material of said second conductivity type in said body region adjacent to said source region and spaced from said diffusion boundary of said body region and said major surface such that the impurity concentration of said portion of said body region is substantially reduced so as to decrease the gate threshold voltage of said trench gate.

14. The method of forming a semiconductor structure as;

set forth in claim 13 wherein step (d) is performed prior to step (c).

15. The method of forming a semiconductor structure as set forth in claim 13 wherein step (d) includes ion implanting material of said second conductivity type in said body region at a predetermined distance from said source region.

16. The method for forming a semiconductor structure as set forth in claim 15 wherein step (d) further including diffusing said compensated portion of said body region in said body region.

17. The method of forming a semiconductor structure as set forth in claim 13 wherein step (d) includes successive substeps of ion implanting material of said second conductivity type in said body region at predetermined distances from said source region.

18. The method of forming a semiconductor structure as;

set forth in claim 17 further including the substep of filling said at least one trench with N-type material.

19. The method of forming a semiconductor structure as set forth in claim 18 wherein step (b) includes the substeps of ion implanting material of said body region in said substrate and thereafter diffusing material of said body region in said substrate.

20. The method of forming a semiconductor structure as set forth in claim 19 wherein step (c) includes the substeps of ion implanting material of said source region in said substrate and thereafter diffusing material of said source region in said body region.

21. The method of forming a semiconductor structure as set forth in claim 19 wherein step (d) includes the substep of diffusing the compensated portion of said body region in said body region and wherein the diffusing of said source region and the diffusing of said compensated portion of said body region are performed simultaneously.

22. The method of forming a semiconductor structure as set forth in claim 21 wherein step (a) includes the substeps of providing a base substrate of said second conductivity type and forming an epitaxial layer of said second conductivity type above said base substrate.

23. The method of forming a semiconductor structure as set forth in claim 22 wherein said first conductivity type is of N-type and said second conductivity is of P-type.

24. The method of forming a semiconductor structure as set forth in claim 23 wherein the implanting material in step (d) is boron.

25. A method of forming a semiconductor structure having a gate with a gate threshold voltage, said method comprising the steps of:

(a) providing a substrate having a major surface;

(b) forming at least one trench in said substrate extending from said major surface;

(c) forming a body region of a first conductivity type in said substrate to a diffusion boundary extending from said major surface;

(d) forming a source region of a second conductivity type in said body layer extending from said major surface; and

(e) compensating a portion of said body region by implanting material of said second conductivity type in said body region adjacent to said source region and spaced from said diffusion boundary of said body layer and said major surface such that the conductivity of said portion of said body region is substantially reduced so as to decrease the gate threshold voltage of said gate.

26. The method of forming a semiconductor structure as set forth in claim 25 wherein step (b) includes the substep of lining said trenches with insulating material and followed by another substep of filing said trenches with conductive material.

27. The method of forming a semiconductor structure as set forth in claim 26 wherein said conductive material is a N-type material.

28. The method of forming a semiconductor structure as set forth in claim 25 wherein step (e) includes ion implanting material of said second conductivity type in said body region at a predetermined distance from said source region.

29. The method of forming a semiconductor structure as set forth in claim 25 wherein step (e) includes successive substeps of ion implanting material of said second conductivity type in said body region at predetermined distances from said source region.