Method of fabricating the high-density diode-based read-only memory device

• US 5,907,778 A
• Filed: 08/06/1997
• Issued: 05/25/1999
• Est. Priority Date: 06/07/1997
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chou, Jih-Wen, Wen, Jemmy
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/907,020
• Time in Patent Office: 657 Days
• Field of Search: 438/130, 438/237, 438/275, 438/276, 438/277, 438/278, 438/587, 438/588
• US Class Current: 438/275
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y10S 257/926 Elongated lead extending axially through another elongated lead

Abstract

A method is provided for fabricating a read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device. The feature size of the ROM device is thus dependent on the capability of the photolithographic process.

Claims

1. A method for fabricating a ROM device of the type including an array of diode-based memory cells, comprising the steps of:

(1) preparing a semiconductor substrate which is partitioned into a memory division and an output division; and

forming a first insulating layer over the substrate and a first doped polysilicon layer of a first type over the first insulating layer;

(2) removing selected portions of the first doped polysilicon layer so as to form a plurality of substantially parallel-spaced data lines oriented in a first direction in the memory division and a plurality of substantially parallel-spaced gate regions in the first direction in the output division, the gate regions being respectively electrically connected to the data lines;

(3) forming a first photoresist layer;

removing selected portions of the first photoresist layer so as to expose selected portions of the first insulating layer in the output division; and

etching away the exposed portions of the first insulating layer in the output division until the substrate is exposed;

(4) with the first photoresist layer serving as a mask, performing a first ion-implantation process on the substrate so as to form a plurality of lightly-doped areas in the substrate; and

removing the first photoresist layer;

(5) forming a second insulating layer over the wafer, both in the memory division and in the output division;

(6) forming a second photoresist layer over the second insulating layer; and

removing selected portions of the second photoresist layer so as to expose selected portions of the second insulating layer in the output division;

(7) with the second photoresist layer serving as a mask, performing an anisotropic etching process on the second insulating layer in the output division, the remaining portions of the second insulating layer serving as a plurality of sidewall spacers on the sidewalls of the gate regions;

(8) with the second photoresist layer and the gate regions as a mask, performing a second ion-implantation process so as to form a plurality of source/drain regions in the substrate in the output division; and

then

removing the second photoresist layer;

(9) forming a third insulating layer over the wafer, both in the memory division and in the output division;

(10) removing selected portions of the third insulating layer and the second insulating layer so as to form a plurality of contact windows to expose a number of selected locations on the data lines that are associated with a first group of the memory cells of the ROM device that are to be set to a permanently-ON state, with the unexposed locations being associated with a second group of the memory cells of the ROM device that are to be set to a permanently-OFF state;

(11) forming a second doped polysilicon layer of a second type over the third insulating layer, which fills up all of the contact windows;

(12) removing part of the second doped polysilicon layer other than those portions in the contact windows, the remaining portions of the second doped polysilicon layer serving as a plurality of plugs respectively in the contact windows;

(13) forming a conductive layer over the third insulating layer, which is electrically connected to the plugs; and

(14) removing selected portions of the conductive layer so as to form a plurality of substantially parallel-spaced word lines oriented in a second direction.

2. The method of claim 1, wherein the first type is N-type and the second type is P-type.

3. The method of claim 1, wherein the first type is P-type and the second type is N-type.

4. The method of claim 1, wherein in said step (1), the first insulating layer is a layer of silicon nitride formed by chemical-vapor deposition.

5. The method of claim 1, wherein in said step (1), the first insulating layer is a layer of silicon dioxide formed by chemical-vapor deposition.

6. The method of claim 1, wherein in said step (5), the second insulating layer is a layer of silicon dioxide formed by chemical-vapor deposition.

7. The method of claim 1, wherein in said step (9), the third insulating layer is a layer of silicon nitride.

8. The method of claim 1, wherein in said step (9), the third insulating layer is a layer of silicon dioxide.

9. The method of claim 1, wherein in said step (11), the second doped polysilicon layer is formed by the steps of:

forming a layer of polysilicon; and

performing an ion-implantation process so as to dope an impurity material of the second type into the polysilicon layer.

10. The method of claim 1, wherein in said step (11), the second doped polysilicon layer is formed in-situ by the step of:

performing a chemical-vapor deposition (CVD) method using SiH₄ and B₂ H₆ as the vapor.

11. The method of claim 1, wherein in said step (13), the conductive layer is a highly-doped polysilicon layer.

12. The method of claim 1, wherein in said step (13), the conductive layer is a metallization layer.

13. The method of claim 1, wherein in said step (14), the second direction is substantially in perpendicular to the first direction.